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Deserializing AFE5808 data on Spartan-6 FPGA

Mariusz Hajduk1
Intellectual 710 points
Other Parts Discussed in Thread: AFE5808, AFE5808A

Hi Everybody,

When clocking the AFE5808 40MSPS everything is fine. However, at 60MSPS the output from FPGA becomes a (unintended) perfect random number generator-:)

Could anybody share the 12/14bit wide deserializer solution for Spartan-6? 99% I'm sure the problem is in timing inside of the FPGA. PCB routing and LVDS termination seems to be OK.

Thanks, Mariusz

  • 0
    TI__Expert 6320 points

    Mariusz,

    The .bit file  for the TSW1250 EVM Virtex-4 is available on the TI website, but I am not sure that you can load this on a Spartan-6.  I am sure that the AFE5808A will work up to 65MSPS as the datasheet says.  If you are using the AFE5808A EVM GUI, I recommend using the Ramp test pattern to debug your project. 

    Can you tell me more about your project?

    Thanks,

    Chuck Smytht

  • 0 in reply to Chuck Smyth
    Intellectual 710 points

    Hi Chuck,

    The bit file for Virtex devices definitely will not work on Spartan. I also do believe that AFE5808 should easily work @65MSPS. That's why I suspect the problem is on my deserializer design inside of the FPGA (timing constraints not met). Yes, I've already used the Ramp test pattern and @40MSPS it works perfect. @65MSPS I have a perfect random number generator -:)) I'm not using EVM, the PCB is my own design 32-ch module for a new ultrasound scanner product under prototyping. The FPGA is located on another PCB, however the LVDS data/frame/bit_clk signals are routed shortly with the equal length of each LVDS pair. 100 Ohm termination is also enabled on FPGA IO's.

    I did't use the FPGA internal ISERDES primitive because it does not support 12/14-bit wide word. All the deserializer I have implemented on FPGA fabric logic. Use an external deserializers for 32 channels is a nonsense!! That's why I'm asking for help.

    Thanks,

    Mariusz

  • 0 in reply to Mariusz Hajduk1
    TI__Expert 6320 points

    Mariusz,

    I am afraid that your above my head on the FPGA side.  Please let me know if I can help more on the AFE side.  Also,  I might be able to find the TSW1250 source code for the VIrtex if that would help you.

    Thanks,

    Chuck Smyth

  • 0 in reply to Chuck Smyth
    Intellectual 710 points

    Chuck,

    If you can find the TSW1250 source code for Virtex, it could be very helpful for me.

    Thanks,

    Mariusz

  • 0 in reply to Mariusz Hajduk1
    Intellectual 710 points

    Hi Chuck,

    Ooopss, I've just clicked wrong button..  In fact, the problem is still 'alive'. I've made some tricks on timing costraint on FPGA. Works @65MSPS a little better, some bits are stable, some not!!  For sure, the problem is not on the TI , also not on a Xilinx !!  The Virtex deserializer source files (VHDL/Verilog) will be very welcome for all the groupers!!

     

    Thanks,

    Mariusz