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Connecting FMC DAC REV D board and DAC34SH84

jas jas
Prodigy 90 points
Other Parts Discussed in Thread: FMC-DAC-ADAPTER, DAC34SH84, CDCE62005

I am trying to do the connections between fmc dac rev d adapter board and dac board.
I wanted to know the difference between the pins labelled IO_DB 15P/N and IO_D15P/N. Similarly for other pins like say IODB_01P/N and IOD_01P/N.
Also, what is the use of pins FPGA_CLKOUTP and FPGA_CLKOUTN?
Also do I need to specify anywhere which pin of fmc connector connected to which pin of DAC using some software like Xilinx Plan Ahead for connections between FPGA and FMC DAC card?

  • 0
    TI__Guru* 78404 points

    Jas,

    The FMC-DAC-adapter schematic can be found on the product folder page:

    http://www.ti.com/tool/fmc-dac-adapter

    Inside the page, the design package has the schematic and layout:

    http://www.ti.com/lit/zip/slor102

    The schematic for the DAC34SH84EVM rev D is attached

    If you trace the pins from the adapter to the DAC board, you will noticed that the IOD bus are for the DAC34SH84 bus AB and IODB bus are for the DAC34SH84 bus CD. Each bus is 16-bit wide, DDR. All the LVDS data are located in connector B and connector C of the HSMC connectors. For instance, IO_D15p/n on the on J2B of FMC-adapter side will connect to DA15p/n of J13B. The same princple applies to J2C of adapter and J13C of the DAC EVM, etc. 

    The FPGACLKp/n are reference clocks from the DAC EVM that you can route to the FPGA board for clocking reference. The reference clock is coming from the on-board CDCE62005. 

    The FPGA pin out configuration can be done after you plan out all the IOs needed for the DAC. This is usually configured by the .UCF file for Xilinx platforms. 

    -KH

    DAC34H8XEVM-SCH_D.pdf
  • 0 in reply to Kang Hsia
    Prodigy 90 points

    Hi Kang,

    Thanks for the reply.
    Do I need to give SYNC and FIFO_ISTR signals also as clocks? Also what about the parity output from fmc card?
    Also, I need to use MMCM from the virtex 6 hdl library or is there some other way too?
    Can you explain the use of pll divider?

    Regards
    Jas