Hello Everyone,
I'm writing in regards to the note in the ads1178 datasheet which says, "For best performance, use fSCLK/fCLK ratios of 1, 1/2, 1/4, 1/8, etc."
I've read other forum questions here in regards to this relationship, but I haven't managed to find one which addresses my concern. My concern is, does this recommendation also suggest a phase alignment between the the two CLK sources to minimize noise in the measurements? In my current design, I operate both clocks at the same frequency, but due to the way that I operate the SPI with DMA on my microcontroller, the time that I activate the SPI CLK (after respecting the tDS specification) can vary slightly, introducing a small phase shift between the two CLK sources between one data read and another (I've never measured more than a quarter of a cycle phase shift between best and worst). Given this, should I expect that this behavior may be introducing added noise to my measurements?
Thanks kindly for any time or insights that anyone could provide.
~Gregg
