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ADS131E04 SPI WREG command - reg shift?

Ireneusz Magiera
Intellectual 335 points
Other Parts Discussed in Thread: ADS131E04

I try to configure ADS131E04. My settings should be:

REG_CONF1 = 0xD1;

REG_CONF2 = 0xE2;

REG_CONF3 = 0xCC;

I have written a function ADS_writereg(uint8_t *buffer,uint8_t startRegAddress, uint8_t regCount) where 2 bytes long WREG opcode is generated like this:
uint8_t bufferTMP[2] = {(startRegAddress | 0x40), regCount-1};
I have defined names for registers like ADS_REG_CONFIG1 is 0x01etc.

When I write my config and read it back I get strange result:

opcode: 11
ADS: d1 e2 cc write: 41 02 d1 e2 cc
OK
read: 20 08 d0 e2 cc 41 00 10 10 10 10

Read data is:
20 08 - opcode RREG startRegAddress 0x00 (ID), regCount=9
D0 - proper ID of ADS131E04 (read-only)
E2 - wrong CONFIG1 data, should be D1
CC - wrong CONFIG2 data, should be E2 like above
41 - wrong CONFIG3 data, should be CC like above
00 - default fault reg value
10 10 10 10 - default settings for channels 1-4

I have noticed recently, that WREG example from datasheet (fig.41) describes writing opcode (OPCODE 1 = 0100 0000, OPCODE 2 = 0000 0001) starting from 0x00 address which is ID register and it's read-only?!
Does it mean that when I pass startRegAddress taken from Table10 to my function I should actually use startRegAddress-1? I can't see that information in datasheet except fig.41 example where read-only ID register is written and I assume someone wanted to write data to CONFIG1 and CONFIG2?

In RREG direct using of startRegAddress seems to work good.

Is it possible to cause any damage by writing improper data to registers? Some of them are described as "Must be set to '1'" and with tries like above this condition wasn't met.

  • 0
    Intellectual 335 points

    I have made some tests and it looks like 1 byte in write sequence is lost.

    I use 1MHz clock for SPI (8clks=8us) so tSDECODE=1.92us is exceeded and communication can be done without additional delays. I have checked on DSO that 41 02 D1 E2 CC are properly transmitted.

    When I write: 41 02 D1 E2 CC and then read back first 9 registers I get:  20 08 D0 E2 CC 41 00 10 10 10 10 (as listed above in my post)

    When I write: 40 02 D1 E2 CC and then read back first 9 registers I get:  20 08 D0 CC E0 41 00 10 10 10 10

    When I write: 42 02 D1 E2 CC (because I thought that missing byte is written to 00h register and because it's read only it's lost) I get: 20 08 D0 91 E2 CC 00 10 10 10 10 where 91 is default value of CONFIG1.

    So I noticed that first byte is always lost. Simple test proved that and when I write: 41 03 FC D1 E2 CC (where FCh is additional, dummy data to lost) I get 20 08 D0 D1 E2 CC 00 10 10 10 10 which is my desired result when I write 41 02 D1 E2 CC...

    So it looks like it's not addressing issue as I thought at first but there is a problem with loosing data. Is there any way to fix that and not provide dummy data?

    My startup sequence is:
    - PWDN=1, RST=1;
    - wait 1s;
    - RST=0;
    - configure SPI + wait 1ms;
    - RST=1;
    - wait 1ms;
    - send SDATAC;
    - wait 10ms;
    - WREG 41 02 D1 E2 CC (now changed to WREG 41 03 FC D1 E2 CC)

    Is anyone able to help?