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Interfacing the TI Concerto F28M36P63C2 to the ADS8556

Marc Zetek
Intellectual 800 points
Other Parts Discussed in Thread: F28M36P63C2, ADS8556

Hi,

We are interfacing the TI Concerto model F28M36P63C2 to a TI ADC model ADS8556. We will be using the 16-bit Host Bus Mode on the Concerto chip for the interface, and we will be using "software mode" on the ADS8556. With these points in mind, I have the following questions:

1. In the ADS8556 datasheet page 27, under the topic heading "Software mode" it says "... CS should be held low during the two or four write accesses to completely update the configuration register...". However on page 28 of the datasheet, the timing diagram shows the CS optionally rising between accesses. Therefore is it really mandatory to hold CS low during the write accesses to the configuration register?

We need to know this, because we need to know whether to tie a chip select line, from the Concerto in Host Bus Mode, to the Chip Select of the ADS8556 (which definitely transitions back high after a write access) or to use an address line, which we can probably force to remain low between the accesses. Please advise.


2. In the ADS8556 datasheet page 29, it discusses Bit C31, C30 and C29 as being able to enable or disable channel pairs "for the next conversion" but otherwise these are not described or discussed anywhere else in the datasheet. It seems strange that zero would be the default, if indeed zero would disable the channel pair for the next conversion.

Please describe these bits in greater detail. If indeed we write zero to these three bits, will the channel pairs be permanently disabled or only "for the next conversion", such that if we put a clock signal (such as a sample clock) on the CONVST bits, it would eventually start the conversion process, regardless of the state of these bits.


3. In the ADS8556 datasheet, it leads us to believe that the internal conversion clock may be used, even in software mode, as long as bit C11 of the configuration register is zero. However, on page 6 of the ADS855xEVM datasheet, it says that "when using software mode, the user must apply an external conversion clock...".

Please clarify whether or not an external conversion clock is absolutely mandatory, or whether it is truly optional based on the state of configuration register bit C11.


Thank you for your helping,

Marc

  • 0
    TI__Guru**** 180961 points

    Hi Marc!

    For your first question, yes, the /CS must be low for the entire configuration write sequence.  Page 28 shows the first configuration sequence covering the entire 32-bit register from C[31:0] while the subsequent writes are only modifying the upper byte (C[31:24]).

    Once disabled, any channel pair would remain disabled until you write to the register again.  The reference to 'the next conversion' assumes you are running the device at full speed and you are writing to the configuration register while a conversion is taking place.  If you disable a channel pair during conversion period '1' for instance, it would disable that channel for period 2, 3...N.

    I'll double check the wording in the Users Guide for the EVM for you as well.

  • 0 in reply to Tom Hendrick
    Intellectual 800 points

    We have done more experiment and determined that indeed chip select may go high in between the 2 writes.

    Absolutely, you can check it by yourself. However, in addition to the chip select being able to go high in between the 2 writes, there are must be some additional timing requirements such as a maximum lenght of time in between which the 2 writes can take place. We can see this clearly in the debugger when we place a breakpoint between the 2 writes.

    Whether we hold chip select low for the 2 writes or not, the breakpoint debugger experiment prooves that there is more going on here than the datasheet suggest.

    You should investigate this further in detail and not believe the datasheet. After you have investigated this further, please reply.

    Thank you for your help,

    Marc