Hello,
i have the RD and CONVST signals of the ADS8363 connected together and them connected to a FPGA.
The problem is now, during init/configuration phase of the FPGA after power up, this signal is first a
digital input signal on FPGA side. So i have two inputs connected together.
Worse is, the FPGA input pin has no pull up/pull down resistor active at this moment.
My question is now, does the ADS8363 have a buskeeper/gatekeeper on its input pins?
This would prevent the FPGA input pin from inadvertently clocking during init.
The FPGA input pin is in this init stage a JTAG TCK input pin ;-)
the ADS8363 -CS is always low in my design.
