Problem of TSW30SH84EVM Lock status

Hi Cheng,

Under the PLL setting of the DAC34SH84 > freq. tune, you have set it to be 9. Most likely the VCO of the on-chip PLL is out of range. You will need to set this to about 32 to center the VCO frequency to be about 3GHz.

The PLL Lock alarm in the advanced page (CONFIG5) will need to be cleared before it updates again for the current status. These alarms will not self-clear upon error recovery because it need to retain the error in between alarm polling intervals. You can check the "clear status" check box to clear alarm and check to see if the PLL LOCK status is cleared.

The PLL lock status in CONFIG5 have a known issue in this silicon that may not accurately detect the PLL lock status properly under certain conditions (documents in the datasheet). The best way is to read back the PLL LF voltage in config0x18 for optimal VCO voltage. Adjust the freq. tune until the PLL LF voltage reads back 3, 4, or 5.

By the way, a nice reference to LMK04808 configuration can be found on page 86 of the LMK datasheet. The condition is very similar to your case.

-KH

Hi Kang:

Thanks for your reply and valuable information.

I tried to set the fine tune as 9 and still no lock at Advanced page. Also I manually cleared and updated alarm status and the result is the same.  The strange thing is that everything looks good if do not enable the DAC PLL and set the CLK4 as 600MHz (DACCLK). If set the DACCLK as 150MHz and enabled the DACPLL, the DACPLL can not really lock as Input page shows lock but the Advanced page does not. And at PLL mode the spectrum is also not good.

Looks like PLL is locked when I played as 80Mhz mode using your configuration file. Could you please modify the configuration file I uploaded to make sure the DACPLL lock?  And then I will test it accordingly here.

Thank you.

Regards,

Cheng

Dear Sir or Madam:

Is there anyone can help out?

Thanks,

Cheng

Hello Cheng,

Could you set the freq. tune (coarse) to be 32 like I mentioned before? By setting the freq. tune to be 32, you center the VCO tuning range to about 3GHz. I was able to get PLL lock on my TSW30SH84 setup.

See attached. Let me know if it works.

-KH

Hi Kang:

Thanks for your information. I tried it, and when I set fine tune as 32, there is no lock. When I set fine tune as 9, the DAC side shows lock, but the Advanced page shows no lock. And looks like the PLL did not really lock. I did uncheck and check the status from Advanced page, it always shows unlock.  I pretty sure the hardware is good, as everything is ok if set the evaluation board as 2.88G

Anything else I could try?

Regards,

Cheng

Hi Cheng,

could you tell me the package label of U1 on your TSW30SH84EVM? Is it DAC34H84 or DAC34SH84?

-KH

Hi Kang:

It is DAC34SH84.

Cheng

Hi Cheng,

I have tested two TSW30SH84EVMs and both of them showed the on-chip PLL locked after loading my register settings. Also, all of the DAC34SH84 devices are tested for PLL lock range during manufacturing. Therefore, I do not think this is a device issue or register setting problem.

On one of the EVMs I do see the on-chip PLL staying locked intermittently after I performed a "read all" event. I suspect the LMK register value might be lost after you perform a SPI register read back. This may be the reason that the DAC34SH84 on-chip PLL not staying locked because the reference clock keeps changing.

Do you have a USB Blaster or Byte Blaster to program the on-board CPLD? If so, you can update the on-board CPLD with the newer firmware. Afterwards, you should be able to see the on-chip PLL staying locked at 600MHz. Instructions and the CPLD firmware are attached.

If not, please private message me and we can discuss about replacement EVM.

-KH

Kang,

I think this response you generated may have been for someone else.

FYI

Pete Harbour

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