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ADC08B3000 synchronization

viswa balaji1
Prodigy 70 points
Other Parts Discussed in Thread: ADC08B3000

Hi,

I have a requirement to use 4 ADC08B3000 ICs. I run each of them at the max sampling rate (3Gsa/s). My design requires that all the ADC ICs start capturing the data at the same time (within < several hundred pico seconds). I may have to place the ADCs on different boards, hence may not be able to use the same Sampling clock. Even if I use the same sampling clock, the cable lengths may not be precise to give me the best possible syncrhonization. I can use the syncrhonize pin of the ADC using the LVDS clock reset pins but I'm not sure what should I reference it to (one of the 4 ADC clocks?). 

I would like to know some suggestions on how to proceed with such a requirement.

  • 0
    TI__Mastermind 44680 points

    Hi Viswa

    To synchonize multiple ADC08B3000 devices two conditions must be met. First the internal CLK/2 of all converters must be aligned using the DCLK_RST function. It is challenging to ensure proper setup and hold timing between CLK and DCLK_RST, but can be achieved if the differential DCLK_RST inputs are used.

    Then during data capture the WEN input of each ADC must all rise simultaneously. The challenge is that this is an LVCMOS logic input, and it will be very difficult to ensure all 4 ADCs capture the rising edge of WEN on the exact same rising edge of CLK (3GHz).

    Regards,

    Jim B