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ADS7886 SCLK duty cycle

Mark Siggins1
Prodigy 20 points

The twH and twL timing requirements are a bit ambiguous: Do they mean that and clock pulse, low or high, only has to be at least 20ns, or do they mean me must maintain the duty cycle to be with 40% and 60%, regardless of frequency?

Or, put another way, if I run SCLK at 1MHz during the conversion, can I still have a clock high pulse as small as 20nS, or does it have to be at least 400 ns?

Cheers!

  • 0
    TI__Expert 5705 points

    Hi Mark,

    SCLK timing must satisfy both the twl spec as well as the twh spec. And since twl + twh = tsclk, this essentially means that  the maximum value of twh (and twl) is 60%*tsclk, even though this is not explicitly specified in the table. So if your tsclk = 1uS then twh (and twl) can vary between 400ns and 600ns. When twh is at its min value of 400ns then twl is at its max value of 600ns and vice-versa.

    Thanks,

    Harsha

  • 0 in reply to Harsha Munikoti
    Prodigy 20 points

    Hi Harsha.

    Thanks for getting back to me.

    I understand, of course, if one is 40% min, the other must be 60%max.

    So really, its the second case that I mentioned. The duty cycle must be between 40% and 60%, regardless of frequency.

    That, and the maximum frequency for SCLK, is all that is needed.

    Thanks again,

    Mark.