Can I get a FPGA source code for ads8568?

Hi Wei Jiang,

I'll assume you are referring to the source code for the Opal Kelly board associated with the ADS8568EVM-PDK, let me see what I can do to get that for you.

Mr Jiang -

You should receive an email shortly with details on how to get the requested information.

Hi Greg,

  Thanks for youe help.

  But the link I seen is empty, like this:

  03/12/2013 02:06下午             22 ads8568evm_fw.zip

  Please check, Thanks again.

  By the way, I'm looking for the source code in verilog or VHDL. I'm not familar with Labview and don't want a Labview vi source.

  My email address is weijiang@ustc.edu,  Thanks again.

Wei Jiang

Mr Jiang -

Please use the link as shown in the email that was sent yesterday.  It appears you have changed the location inadvertently to point to an invalid location.

HI Greg,

  I am also using this ADS8568 ADC with spartan 3 FPGA. I have done Schematics And now i want to write verilog code  for the reading data.

 Could you please help me by providing the vhdl code to me if possible.

Thanks and regards

Sumit Sharma

Sumit -

Can we use the email associated with your TI account for sending you the information?  If this is not the best email account, please let us know the preferred contact method.

Hello Greg,

    You can share the code on xxxx@gmail.com.

Thanks

You should receive an email shortly with the requested information.

Hello Greg,

   I am able to download the code . But there is nothing in the folder. and also the size is 22 bytes only. Could you please send me the code again.

Thanks

Please retry the download...the file has been updated

I am using the ads8568evm for our project.  Could you also send me the password for the FPGA  source code( ftp://ftp.ti.com/pub/data_acquisition/ads8568evm_ fw.zip) a. This is my email address:  xxxx@163.com,   Thank you very much!

You should receive an email shortly with the requested information

Hello Greg,

     We are planning to control ADS8568( in parallel mode) with a small CPLD (32 I/Os). like all control signals will interface with CPLD and  FPGA will  read  DATA only .

    There are some I/O pins interfaced between CPLD and FPGA. When the conversion will be finished then CPLD will give an indication of EOC to the FPGA through I/O  

    pins.   (Like channel information, Sampling clk  etc.).  

 Is it Possible to have such kind of interface? Can we able to read the data from FPGA ?

 Please give your feedback.

Thanks

Sumit Sharma

Mr Sharma -

This seems like a very complex solution, unless you are short on pins.  However, as long you can meet the timing in the datasheet, there shouldn't be issues with controlling the device using different chips.  Just make sure that you perform thorough testing (over time) to ensure that you don't get out of sync or create some kind of invalid case at some point in your code.

Hi,

Could you also send me the vhdl source for ads8568 to my account email?

You should receive an email with the requested information shortly.

Hello Greg,

If I may receive the HDL source code for the ADS8568 interface to the assoiciated e-mail,

that would be a big help.

Thank you,

Mr Castiglia -

You should receive an email with the requested information

Hi Greg,

 Could you please send me the vhdl source or password for ads8568 to my  email?  kraikook@hotmail.com

I'm already download ads8568evm_ fw.zip, but cannot unzip.

Thank you,

hallo Greg Hupp'

I wold like to get the password enter to for ads8568evm_ fw.zip

my mail maorivni@gmail.com

Thanks in advance.

Hello Matt,

You should receive an e-mail shortly.

Best regards,

Jose

Hello Luis,

Please download the ads8568evm_fw.zip file available at

ftp.ti.com/.../

I will send you the password to unzip the file via e2e private message.

Best regards,

Jose

Hello KB,

Please follow the instructions above.

I will send you the password to unzip the file via e2e private message.

Best regards,

Jose

Hello,

May I ask for the password for the ads8568evm_fw.zip file? The email in my profile is valid.

Mira Sliva