DDC114 transient response characteristics

Hi,

I do not have the experience with this myself so, the following is just a guess...

I think a portion of the transient current from the photodiode will flow into the feedback capacitor of the integrator (where you expect it to go) and a portion into the parasitic capacitance of the photodiode itself and the input (device and trace). The ratio basically depends on how fast the input amplifier is. Nevertheless, this may be ok... I believe that the charge that gets stored on the parasitic elements will flow back into the input as the amplifier loop is catching up and trying to set the virtual ground. I have seen that in other charge amplifier. I think the amplifier will be fast enough for all that charge to be collected back into the integrator (more than lost to leakage). The only concern is that during that transition, as the charge gets stored in the input capacitance, a voltage will be built at the input. If that voltage turns on the protections (see page 9) then you will lose charge/signal. Also, I have not found what is the input current limit on the device, but from other DDCs, that is usually like 1mA or so, so, try not to get close to that...

Finally, digging around I also found this previous answer, which seems to be pointing to something similar:

"We have had other customers use DDCs with Linear Accelerators that deliver energy in ~4us pulse.  I haven’t heard any issues.  There isn’t anything in the datasheet about this partly because we have no way of testing this today.  The capacitance at the input to the DDC may actually help in this case because if the DDC can’t fully keep up with the current pulse then charge builds up on the input capacitance.  As long as the short pulse is done at the beginning of the integration period the charge that has built up will have plenty of time to settled by the DDC.  The input circuitrys bandwidth changes with range and sensor capacitance.  With small censor capacitance the bandwidth is ~1MHz."

Hope this helps,

Edu

I am evaluating the DDC112 for a similar pulse mode application.  The data sheet is silent about the bandwidth and transient characteristics of the op amp.  Eduardo mentioned previously that the bandwidth was ~1MHz for "small" sensor capacitance.  Can you tell us from the design of the part what you'd expect for moderate sensor capacitances, say up to 200pF?  I'm concerned about three things:  1) settling time, 2) transient behavior briefly saturating the op amp input stage, and 3) transient behavior turning on protection devices.  Black box testing doesn't tell us how close we are to these issues affecting performance, so I'd to know more about the op amp to model things.

A related issue is when a narrow input pulse edge coincides with a CONV edge.  The data sheet doesn't give timing information about switching the analog input between the A and B integrators.  Whether the action is break-before-make (more likely), make-before-break (undesirable), or perfectly synchronized switching (unobtainable), there is going to be a small window when the input switch state is undefined.  How wide is that window, approximately?  If this hasn't been characterized, I would be happy with an approximation from the design of the part.

Sorry for late answer... On the first paragraph, we do not have any extra information... As explained, this is a mode that we have not characterized the device for and being the DDC112 an old device, it would require a quite a bit of effort to do so (run some sims in an old database) I would recommend you to get one of our dev kits and check it under your particular conditions...

On the 2nd portion, going by the DDC264 (newer device) we believe that DDC112 will be a break before make. The time between the two instants will be a few nano-seconds. No charge is lost in this time as it is stored on the sensor cap and goes to the other side once it turns on. Again, we don't know what exactly happens for DDC112.

Best regards,

Edu

Thanks for the reply.  The DDC114 seems more likely at this point.

The main question at this point is the data sheet graph for the DDC112 showing noise increasing as integration time gets longer when there is significant sensor capacitance.  The graph for this test in the DDC114 data sheet is flat over the integration time shown.  The time scale on the DDC114 graph is 100 nanoseconds to 1 millisecond, rather than the 100 microsecond to 1 second range for the DDC112.  Given that the part has two integrators in order to integrate continuously, and the ADC is too slow for this to happen at any of the times shown in the DDC114 graph, I'd like to believe this axis label is simply a typo.  If so, the DDC114 has different noise properties from the DDC112 in an important way.  Can you tell me anything about this?

A related question is that the data sheet only shows noise vs integration time for one of the least sensitive ranges for the part.  For low-noise systems, the most sensitive ranges are more important.  I could imagine that the increase in noise at longer integration times could be worse, and start sooner, with smaller integrator capacitors, but I can only guess.  Whether this happens or not in the DDC114 is important, and if it does, at what integration time does it begin to increase at?  The particular conditions are up to 200pF sensor capacitance using the 12pC range.

I know these parts are older.  Our TI field engineer says the part is still listed for new designs, so I'm hoping there's some insight TI can provide.  Characterizing a black box part like this ourselves requires a test setup that is capable of reaching the device noise floor.  If your EVM hardware and software can't reach the device noise floor, we'd have no way to characterize the part except to fully design it into the product.

Thanks again for your help.

Seth,

I believe you sent a representative some similar questions. I sent a response to these a few days ago, hopefully it has been forwarded to you already. 

There is no typo in the DDC114, the data shown is correct. As the data sheet doesn't show the rest of the time scale that the DDC112 shows, we cannot be sure of the noise performance over larger TINT values on the DDC114.

As for the other range data, this is also not known for sure since characterization focused on the more popular ranges at the time (the higher ones). We can assume that given your mentioned input capacitance and range selection, you should see a baseline noise of approximately 68.1 PPM RMS (from the Noise vs Csensor table).

Please let me know your thoughts,

-Adam Sidelsky 

Adam,

Thanks for the information.  The TI field engineer did send me a reply and I'm glad I now know where it came from.  I appreciate you looking into it and taking the time to reply.

We did see, before making any inquiries, the chart in the DDC114 data sheet that lists noise as a function of sensor capacitance, and the graph in the DDC112 data sheet that gives the same information. The conditions used in the DDC112 graph had very low noise gain at the amplifier input.  Specifically, the high frequency noise gain was only1.8 (50pF sensor capacitance, 62.5pF integrating capacitor).  The noise increase from 1 msec to 1 second integration time was only 35%.  That is quite impressive and I'd be happy with that result.

However, we are proposing to operate at 200pF sensor capacitance and a 3pF integrating capacitor.  This has a high-frequency noise gain of 68.  It seems risky to assume that the noise increase for long integration times with this high noise gain would be similarly low as with low noise gain.  While I might guess that the noise increase has to do with 1/f voltage noise at the amplifier input and possibly 1/f current noise in the input switches, this doesn't help predict the result under high noise gain conditions.

As I mentioned previously, I've heard that the EVM for the DDC112/114 cannot reach the device noise floor.  If I am mistaken in that belief, please let me know.  If the EVM noise floor is above that of the part itself, measuring noise versus integration time using that board would not answer the question.  I'd be happy to tell you more about the application if we can do this offline.

Seth,

You can email me at adamsidelsky@ti.com and we can discuss further.

Regards,

-Adam