DAC for FMC on Xilinx ML605

Tobias,

The DAC34H84 and DAC34SH84 would be good solutions for your application. we currently do not have reference design for Xilinx Virtex 6 series. However, you may refer to the app note below for Altera FPGA reference design code as a starting guideline. 

http://www.ti.com/analog/docs/litabsmultiplefilelist.tsp?literatureNumber=slaa545&docCategoryId=1&familyId=2023

Due to the mechical layout of the adapter boards, the FMC-DAC-Adapter will fit on the HPC port on the ML605, while the FMC-ADC-Adapter will fit on the LPF port of the ML605. See attached picture for example connection of our DAC3283/ADS62P49 TSW4200 Evaluation Platform. 

The DAC34H84/SH84 EVM are assembled with the DAC34H84/SH84 silicon. There is no need to solder the device yourself. 

-KH

Hi,

thank you very much for your answer. I've got another question concerning the interface. You said that "the FMC-DAC-Adapter will fit on the HPC port on the ML605".

Is the reason for using the HPC connector only the mechanical issue that the card will block HPC-Port if connected to LPC? Or are there pins used/functionality needed that are only provoided by HPC? In the data sheet/schematic of the FMC-DAC-Adapter there are only 160 pins which also seem to be provided by LPC, aren't they?

To put the device into service I will have to follow the instructions from the DAC's data sheet ( http://www.ti.com/lit/gpn/dac34h84), right? I am not completly aware of how to distinguish whether the words sent are control or data. Data will be fed by setting A&C words to D[15:0]&DB[15:0] of the FMC during rising edge of data_clock ( = EXT_DCLK_P/N in FMC?) and B&D to the same inputs during falling edge. To clear the fifo regularly, sync pin is set to 1/2 of the frequency of data_clock, right? But how can I indicate control words to write to/read from registers? I don't see any pins left on FMC Connector.

In the EVM's user guide, the DAC is configured only via USB from a PC. Or is that configuration persistent and must only be done once on the PC to make it run with a FPGA attatched only later on?

Thank you, kind regards

Tobias Rueckelt