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Achieving optimal gap between read and write pointers when in dual sync mode

Andrew Do
Prodigy 90 points

Hi

In reviewing the synchronization application note (Posted by on Mar 07 2013 14:29 PM) I have the following concern/question

This might be alleviated with custom hardware, but currently we have a single FPGA development board connected to 2 TI DAC boards. The startup time between the FPGA and DACs is arbitrary and not linked. The DAC's are linked to the same clock and OSTR, but will have a slight phase offset due to non matching trace lengths (not a concern). The FPGA also has a reset button which might be used at times.

My concern is how to achieve ~4 position spacing between the FIFO's read and write pointers when using the dual sync method. Since the two sync strobes are totally independent of each other and neither can be controlled, or initiated by the other (based on the available connectivity) I cannot determine how I can naively guarantee the spacing.

The app note discusses checking the alarms and tuning the offset adjustment. I don't believe that there is feedback to state the actual difference between the read and write pointers, and thus I have a concern, which is discussed briefly in the app note, that the initial config (or the config that is settled upon after tuning on startup) is on a threshold and corruption occurs at a later time due to 'PVT'.

I suppose I could tune the offset adjustment to intentionally have collisions occur and then set the final offset to '(collision offset + 4) mod 8'..

Is there a recommended method?

Thanks

Andrew

  • 0
    TI__Guru* 83215 points

    Hi Andrew,

    Since you are using dual sync sources mode, I am assuming you are trying to synchronize multiple DAC devices. In order to achieve synchronization at the multi-device level, the DACCLK and OSTR signals to the devices must have the same delay. Per the requirements of multi-device synchronization, this should be a concern for multi-DAC synchronization since any delay mismatch will translates to FIFO read time difference, and causes latency to change.

    The idea is to use the FIFOs to absorb any latency variation at the FIFO input side to ensure the DACs have the same latency at the FIFO output side.

    If you are not concerned about multi-DAC synchronization, then you should follow the section on "Optimize FIFO Location for Single Sync Source Mode". The section talks about the purpose and procedure to achieve 4 position spacing between the FIFO input and output pointer. The DAC does not have the ability to read back the actual FIFO input/output pointers position directly (since they are always changing if the DAC is running), however, the alarm register in CONFIG5 will indicate the relative FIFO pointer positions. One example of FIFO offset adjustment algorithm shown in Figure 19 shows a way to optimize FIFO location. If the inital start-up offset is not optimal, you may need to intentionally collide the FIFO pointers to get the feedback for optimization. There are other, more efficient ways as well, and the app note shows the simplest way for demonstration purpose.

    Ultimately, if there are latency variation at the FIFO input side, it is not possible to achieve 4 position spacing AND multi-device synchronization since the FIFO has to absorb the latency difference between the two devices. This is the reason that the app note described two methods for optimizing the FIFO location, and it is up to the end user to choose the method based on their end application. If there are *no* latency variation at the FIFO input side, then you can achieve the both scenarios.

    -KH