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need help for an Adc evm

Simone Piccirilli
Prodigy 230 points

Other Parts Discussed in Thread: THS4503, THS4509, ADS5541

Hi at all,

I'm working on a project regarding optical communications. I'm using a Fpga, that prepares digital data for a high speed DAC and should be capable to read an analog signal from a photodiode. For my project, and devices rates, I need an ADC board that is capable to:

1) read DC signals;

2) have a digital output interface on a n-pin header;

3) have a sampling rate of at least 100 MSPS.

I found some boards, like ADS5424evm or ADS5541evm , but I need to be sure that they cover the points above, the first one principally.

Thanks in advance for all your help and every your suggestion.

Bye

Simone

  • 0 in reply to Matt Guibord
    Prodigy 230 points

    Hi Matt,

    thank you for the support.

    I'm reading some data sheets about the ads5424evm and related components, just to understand how it works.

    On section 2.2.1, point 2, page 7, of the datasheet there's the possibility to have a differential input to the adc via the operational amplifier ths4503. Watching the schematic of the board on page 18, it seems to me that the configuration of the amplifier is for dc-coupled signals (no series capacitor).

    Moreover, on page 18 of the datasheet of the chip ads5424 , there's a point in which it says that, for a dc-coupling configuration, I could use a differential input via ths4509. On fig. 41, page 19, of the same datasheet, there's a configuration of this amplifier that is similar to the configuration of the ths4503 on the ads5424evm. The difference between ths4503 and ths4509 seems to me to be the bandwidth and some other parameter.

    What I'm not able to understand is the maximum input voltage range that I can apply to the input J10 of the evm. For the input on J11 I can supply max 2.2 Vpp: is the same for J10?

    Another question regards the input clock to the board. On section 1.4.4, page 6 of datasheet, it says that the input clock source should be 1 Vrms, 0 V offset and with impedance 50 Ohm . If I watch the schematic, there's a transformer after the clock input J5. What happen if I use a source at high impedance? I suppose that with a transformer, I can use also an offset. Anyway, if I have an unbalanced signal, for example a sinusoidal signal with an offset, what happen? Could this damage the device?

    Thanks for your help and every suggestion.

    Ciao

    Simone

  • 0 in reply to Simone Piccirilli
    TI__Intellectual 780 points

    Simone,

    1) As said, already answered.

    2) If you open tool pages you will find user guides there. Both tools have parallel interface if you are asking for this.

    3) All you need to do to find answer for this question is to find chip product page. The ADS5424 and ADS5541 have maximum conversion rate of 105MSPS.

    Simone Piccirilli said:
    On section 2.2.1, point 2, page 7, of the datasheet there's the possibility to have a differential input to the adc via the operational amplifier ths4503. Watching the schematic of the board on page 18, it seems to me that the configuration of the amplifier is for dc-coupled signals (no series capacitor).

    This is correct.

    Simone Piccirilli said:
    Moreover, on page 18 of the datasheet of the chip ads5424 , there's a point in which it says that, for a dc-coupling configuration, I could use a differential input via ths4509. On fig. 41, page 19, of the same datasheet, there's a configuration of this amplifier that is similar to the configuration of the ths4503 on the ads5424evm. The difference between ths4503 and ths4509 seems to me to be the bandwidth and some other parameter.

    This is also correct.

    Simone Piccirilli said:
    What I'm not able to understand is the maximum input voltage range that I can apply to the input J10 of the evm. For the input on J11 I can supply max 2.2 Vpp: is the same for J10?

    ADC chip has 2.2 Vpp Differential Input Range. The J10 is non-differential (single-ended) input. You need to calculate the maximum voltage range. This might be helpful: http://e2e.ti.com/support/amplifiers/high_speed_amplifiers/f/10/t/257522.aspx Please note that amplifier has VOCM signal that is basically VREF in this application.

    Simone Piccirilli said:
    Another question regards the input clock to the board. On section 1.4.4, page 6 of datasheet, it says that the input clock source should be 1 Vrms, 0 V offset and with impedance 50 Ohm . If I watch the schematic, there's a transformer after the clock input J5. What happen if I use a source at high impedance? I suppose that with a transformer, I can use also an offset. Anyway, if I have an unbalanced signal, for example a sinusoidal signal with an offset, what happen? Could this damage the device?

    Small offset will be acceptable but we do not want to heat transformer. Please search for "transformer unbalanced to balanced". Impedance of 50 [Ohm] is standardised, you should not have issues matching it. There is a lot of theory around impedance matching. Fortunately internet is full of it.

    If you are not sure, ask someone. For sure you have some supervisors at the university.

  • 0 in reply to Maciej Kucia1
    Prodigy 230 points

    Perfect,

    thanks for your quick reply.

    Best Regards.

    Simone