Other Parts Discussed in Thread: AFE7071, CDCM7005
Is there anything you can tell me on how jitter on the sampling clock affects the AFE7071's operation?
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Hi,
Attached is a phase noise measurement result from AFE707xEVM, which includes DAC clock jitter and phase noise of local oscillator. As long as you provide a proper DAC clock, it does not impact on any functional operation. With better DAC clock jitter, you'll get a better phase noise.
Thanks,
KW
8420.AFE707xEVM_PhaseNoise.pptx
Also, please review the EVM design, as there is a CDCM7005 Jitter Cleaner for the CLK. I recommend using this if there is any question about CLK jitter from the CLK source. http://www.ti.com/litv/pdf/slou337
-Leonard
ACAT Dallas
Hi, there is also a pretty good appnote which looked at how clock jitter or phase noise affect the Noise Spectral Density of the DAC output signal.
http://www.ti.com/lit/an/slaa566/slaa566.pdf
There are also a few examples of how to spec the DAC clock phase noise assuming some performance parameters such as % EVM (inband noise) or ACPR (out of band noise), assuming the system is noise limited and not distortion limited.
Ken