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ADS5402 test patterns

Alexey Fedorov
Prodigy 30 points

Other Parts Discussed in Thread: ADS5402, ADS5400

Gentlemen,I have yet another question about interfacing with ADS5402.

Datasheet (last version of 4 Mar 2013) describes that custom test patterns (3 words) is available only. But I installed GUI (without evaluation board) and found setting which enables PRBS test pattern. It is controlled by bit 4 of addr 0x2 (which is always 0 in datasheet registers description). Does it really present? What sequence is used: polynomial type, distribution between data bits (or all bits are same?), e.t.c.

Could you provide more details, please?

  • 0
    TI__Mastermind 29220 points

    Hi,

    That feature is real, but ended up not being chosen for inclusion in the datasheet.  if this feature is not added to the data sheet then I may have to remove the feature from the SPI GUI.   This feature has been in a few of our recent high speed data converters such as the ADS5400, but I have not seen that much customer interest in the feature.  The pattern is a standard 2**7-1 PRBS pattern, one that is used in many types of communications equipment and is pre-programmed in a lot of test equipment such as Bit Error Rate Testers. 

    From the ADS5400 datasheet for example:

    The PRBS output sequence is a standard 27-1 pseudo-random sequence generated by a feedcack shift register where the two last bits of the shift register are exclusive-OR’ed and fed back to the first bit of the shift register.  The standard notation for the polynomial is x7 + x6 + 1. The PRBS generator is not reset, so there is no initial position in the sequence. The pattern may start at any position in the repeating 127-bit long pattern and the pattern repeats as long as the PRBS mode is enabled. The data pattern from the PRBS generator is used for all of the LVDS parallel outputs, so when the pattern is ‘1’ then all of the LVDS outputs are outputting ‘1’ and when the pattern is ‘0’ then all of the LVDS drivers output ‘0’. To determine if the digital interface is operating properly with the PRBS sequence, the user must generate the same sequence in the receiving device, and do a shift-and-compare until a matching sequence is confirmed.

    One difference with the ADS5402 and the previous PRBS features on other devices such as the ADS5400 is that this time we made the PRBS output be shifted by one clock on each of the LVDS outptus to avoid simultaneous switching noise.

    Perhaps the best description is a screen capture of the bits display from the TSW1400 when the PRBS mode is enabled, please see attached.  There you can see the repeating 127 bit pattern output on each position of the 12 bit sample output.

    Regards,

    Richard P.

  • 0 in reply to Richard Prentice
    Prodigy 30 points

    Thank you very much!

    I think the feature should be useful for high speed interfaces because two constant patterns are insufficient in some cases. Because they allows transitions 0-1-0-1... only

    1) PRBS allows to check data integrity  for various signal transitions.

    2) I'm planning to use SERDES with DPA feature on FPGA side  to receive 800 MSPS data from ADC. PRBS patterns allows to check and compensate bit shifting between data lines which can appear with DPA.

  • 0 in reply to Alexey Fedorov
    TI__Mastermind 29220 points

    Hi,

    You're welcome.  By the way, when we were designing the TSW1400 Capture Card, we stayed away from using the dynamic phase adjust feature in the FPGA since in the presence of a small signal input there can be some most-significant bits that rarely or never toggle and there would not be anything for the DPA to adjust to.  800Mbps was a very achievable data rate for LVDS DDR into input DDR cells (not SERDES)  so we did not need to use DPA anyway.

    Regards,

    Richard P.