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ADS1675: CLK, AVDD, AGND

Brian Lewis
Prodigy 50 points
Other Parts Discussed in Thread: ADS1675

I am looking at the reference design of the ADS1675.  The input CLK pin specs a voltage up to AVDD, but the reference design uses a 5V digital supply for the level translating buffer.  Also, the power supply for pin 53 (AVDD) calls out the 5V Digital supply.  All other AVDD pins are tied to the 5V analog supply.  As such, here are my questions:

Are pins 53 and 54 electrically connected to the other AVDD and AGND pins?

Should they be hooked up to digital or analog supplies?

Thanks,
Brian 

  • 0
    TI__Mastermind 23235 points

    Brian -
    So all the AVDD pins should be tied to the same voltage potential.  However, AVDD pin 53 is the supply for the clock buffers, which may feedback some noise and degrade performance of the device.  We recommend that you keep it separated (decoupled Y connection) from the remaining AVDD pins.