Hi,
If I assume the fCLK is 2.048MHz, and by following the example in datasheet for the equation 6, the minimum SCLK speed should be 1.75MHz, not 1.72MHz.
Is it correct?
Thanks,
Ming
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Hi,
If I assume the fCLK is 2.048MHz, and by following the example in datasheet for the equation 6, the minimum SCLK speed should be 1.75MHz, not 1.72MHz.
Is it correct?
Thanks,
Ming