DAC3482EVM configuration issue using EVM GUI (App controls in a "stuck" state)

Kang,

Thanks for the feedback.  I have made some progress, but still have 1 main question.  I was having a little trouble getting the DAC3482 chip to talk through the serial interface and this was a wiring issue on the EVM.  I have resolved that now and I am successfully programming both the CDCE62005 & the DAC3482 via a serial interface I have instantiated through an FPGA.  I am attempting to get the HW setup TI has described as "Interfacing Altera FPGAs to ADS4249 and DAC3482" (document SLAA545) running with an Altera FPGA [ ADC --> FPGA --> DAC ].  The documentation and FPGA source code TI has provided has been helpful.  There is one aspect of the signal interface I still do not understand though.  TI provides three documents on this topic

- "Interfacing Altera FPGAs to ADS4249 and DAC3482" pdf document

- Altera QAR file that offers FPGA source code providing a "pass through" clock - bus system from ADC - to - DAC (ads4249_dac3482_interfaces.qar)

- example configuration files for the DAC3482EVM [DAC + CDCE] (TI_CDCE62005_PLL_Configuration_ADC-FPGA-DAC.zip)

My question is related to your review of the DAC FIFO synchronization method I first suggested.  The example chip config file (TI_CDCE62005_PLL_Configuration_ADC-FPGA-DAC.zip) utilizes the DAC FRAME signal to sync the DAC FIFO's input side & the input logic Data Formater.  But, the FPGA source code only provides "sync" configured as an FPGA output signal to the DAC.  How should I connect this to the DAC to support DAC synchronization?  The DAC3482EVM diff signal pair named "FIFIO-ISTR" is routed to FPGA input pins, not output; so I am thinking this signal must be for the TI TSW product instead.  Should I route this "sync" signal for the DAC FIFO input side to the SYNC HW signal or to the FRAME HW signal?  It is exactly how to synchronize the DAC FIFO with the FPGA source code that has me confused.

I understand this signal (sync) will align the DAC input FIFO to a DATACLK edge and the OSTR signal (from the CDCE62005 system clock source) will align the DAC output FIFO with DACCLK.

Any insight on this would be helpful.

Thanks,

Pete

Pete,

The FIFO and clock divider can be programmed to listen to either the rising edge of FRAME or rising edge of SYNC. In terms of synchronizing the FIFO and clock divider, there are no differences between the two signals. The design team leaves the options to the user in case there are some PCB routing advantages when choosing the signals. In your case, you should map this to a valid FPGA output connecting either to FRAME or SYNC instead, and make sure the DAC GUI has the corresponding setting.

The SYNC signal does provide additional functionality in terms of synchronization multiple DAC chip's on-chip PLLs. If your application requires synchronizing multiple devices with on-chip PLL enabled, then you will need to make sure that the SYNC signal is routed accordingly.

-KH