Can JESD204 interface provide deterministic sample time?

When using the JESD204 interface, is the actual time that a sample is taken deterministic or is the latency variable?  The application is a form of oscilloscope and the time from when a sample is captured to when it's available on the internal bus of the receiving FPGA needs to be a known constant.  Since the serdes interfaces have buffers, bit slipping, etc, is the latency fully deterministic or will varainces in voltage, temperature and device skew that timing?