This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADC/DMA configuration

Hi,

I am having trouble to configure the ADC to work with the DMA on the SM470R1B1M. The ADC is configured in buffer mode, FIFO size 64 words. The ADCLK = 30MHz.

To get 500KHz as sampling frequency, the SW is set to 40.

ADC configuration:

ADCR1 |= PS_1; // ADCLK prescaler = 1
ADSAMPEV |= SEN; // ADCSAMP1 controls SW
ADSAMP1 = 38; // SW = 38+2

ADBCR1 = 0x0000; // BNDA = BNDB = 0
ADBCR1 |= BUF_EN; // Buffer mode enabled
ADBCR2 = 0x2; // BNDEND = 010 => 64 words (the MAX availabled on the SM470R1B1M)
ADBCR3 |= G1_DMA_EN; // Group 1 DMA enabled

ADCR2 |= G1_MODE; // Continuous Conversion

// TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference
// Guide, pag.65

// Analog-to-digital converter enable.
// When this bit is cleared to 0, the ADC state machine is
// in idle state. While the ADC EN bit is cleared, the inputselect
// registers (ADEISR, ADISR1, and ADISR2), and
// the status register (ADSR) are held at their reset values.
// When ADC EN = 1, the ADC state machine is released,
// which allows normal ADC operation to start.
ADCR1 |= ADC_EN; // Enable ADC

// Pin ADIN6
ADISR1 = (1<<6); // Convert group 1 = channel 6

------------------------------------------------------------------------

DMA configuration:

// DMA transfer is done through Channel 4 (ADC G1/MibADCDMA1) using Control
// Packet 0

// Control Packet 0
// Interrupt enabled = 1
// Transaction Access Size = 16 bits
// Destination Increment = 1
// Source Increment = 0
// Destination Module = memory select 2
// Source Module = peripheral
DMAC00 = 0x0000A84E;
DMASA00 = (uint32)&ADBUF1; // ADC Group 1 FIFO buffer
DMADA00 = dest;
DMATC00 = 64; // The number of DMA transactions to be completed.

// Channel 4
// Interrupt level = 0
// Suspend enable = 0
// Request enable = 1
DMACC0 = 0x00020000;

// Control Packet 0 is updated and will be used for transfer.
DMACPS = 0x00000001;

DMAGC = 0x00000000;

// DMA halt disabled
// DMA stop disabled
DMAGD = 0x00000000;

DMACCP1 = 0x40; // DMAEN4 set to 1

The DMA interrupt (CIM_DMA0) never goes OFF, the data is not read out into the application buffer. When I pause the debugger the registers show that the ADC overruns:

ADBUFST: 
G1_EMPTY = 0
G1_OVR_FLAG = 1
G1_INT_FALG = 1

ADSR:
G1_END = 1
G1_BUSY = 1

Is there anything obviously missed? or wrong?

Thanks,

Giuseppe

  • Giuseppe,

    Unfortunately, I am not an expert with the DMA/ADC.

    However, after looking through your code, I do not see where you enable the ADC.

    I believe this should be set with ADCR1.

    I expect you are setting it, as you get an overflow.   Can you send your code to my email address, and I can look in more detail?

    Regards,

    Wade