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What determines ADS1299 tCLK (Master clock period) Range?

Conor Russomanno
Prodigy 10 points
Other Parts Discussed in Thread: ADS1299

Hi there, 

I'm working with the ADS1299 chip and trying to interface it with an Arduino library that I'm building. I've been searching through the datasheet for what determines the tCLK master clock period, but can't seem to find it. I see that the range is from 444 ns to 666ns. Is that range linearly mapped to the DVDD supply (2.7 V < DVDD < 3.6 V) shown at the top of the column of Figure 1 (Timing Requirements) on pg. 8 of the datasheet?

If somebody could help me with this one, that would be great.

Thanks in advance.

Conor

  • 0
    TI__Guru 66806 points

    Hi Conor,

    Welcome to the TI E2E forums!

    The internal clock for the ADS1299 is not a parameter that the user can control. The device is trimmed to have a nominal frequency of 2.048MHz (tCLK = 488 ns). The range for tCLK that you see in the Timing Requirements table is the allowable tolerance on this spec and it is not linearly mapped to the range of DVDD.

    The same allowable range for tCLK is valid when using an external clock as well. 

    As you look through the Theory of Operation section of the datasheet, many of the important timing specs are simply expressed as functions of tCLK.

     

    Regards,