LM97600 design approach of connecting to FPGA Virtex6

Hi Ryuji

The Virtex 6 should work just fine as long as it has the necessary number of GTX transceivers (10) available to receive the LM97600 data. The FPGA will need a reference clock that is synchronous to the ADC sampling clock, but at a lower frequency. On the evaluation board we use a 2.5 GHz ADC clock, and a 200 MHz reference clock for the GTX transceivers. The GTX clock input port for the reference clock will be determined by the GTX transceivers that are used for the serial data signals.

The LM97600RB evaluation board uses a Virtex 5 and the design should be very similar using the Virtex 6. The complete documentation package for the LM97600Rb can be downloaded here: http://www.ti.com/litv/zip/snar030

The serial data signals should be AC coupled as in the evaluation board. The capacitors used should be very small to minimize impedance changes at the capacitor pads. The trace pairs should be 100 ohms differential. The signals should be routed to avoid sharp bends and other causes of impedance discontinuities. If the signal pairs must change layers in the board controlled impedance vias should be used, and they should add vias connecting ground planes near the signal vias used to transition between layers. An example of this is shown in the evaluation board design. It is preferable to only route the high speed traces on the top or bottom layers of the board to eliminate via stubs. If the serial signals must be routed on an internal layer. the vias used to transition from the external layer to the internal layer should be 'back drilled' to eliminate the via stub. See this link for more information on this topic: http://www.polarinstruments.com/support/si/AP8166.html

The high speed serial traces require a continuous ground plane as reference. The traces should not cross any gaps in the ground reference plane.

I hope this is helpful.

Best regards,

Jim B