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vsp2566 AFE/CCD questions

Ray Schumacher
Prodigy 20 points
Other Parts Discussed in Thread: VSP2566, CDCE913

To interface the vsp2566 to a TC237 or TC253 CCD (or any other), how is the H/V pixel count set? Ie, to properly set OB via the leading, trailing pixels per line,  and blank lines, it seems that the AFE needs these values set in a register (?). I've read the PDFs and the block diagram pages, but it still isn't quite clear.

Are there reference circuits for the vsp2566? DSP code?

 

  • 0
    TI__Expert 3370 points

     

    The VSP2566 does not contain a timing generator, so it does not have the concept of horizontal and vertical pixels. The VSP2566 does recognize different types of pixels

    • Image pixels - normal mode, it will digitize these after performing optical black correction, gain ,etc
    • Optical black pixels - Used to establish a reference level for pixels with no light
    • Clamp Dummy - used to periodically reset internl biases, on a CCD these are pixels which are not used. Often these are horizontal transfer gates only.
    • PBLK - Blanking funtion - forces the digital outptus to zeros. Often used with CLPDM and/or CLPOB to prevent sending non-image data to the digital processor.

    A CCD may have multiple instances of different pixels on a single row. As an example, there may be optical black pixels at the beginning and the end of a row of pixels.

    The external timing generator is responsible for tracking the locations of these differnent pixel types and applying the correct signals at the correct time to the CLPOB, CLPDM, PBLK, etc pins of the VSP2566. These general considerations apply to all imaging AFEs with external timing generators. THe attached diargam demonstrates when to apply these signals as a function of CCD pixel type.

    For AFEs with an internal timing generator there are registers which allow one to set Horizontal and Vertical pixel counts as well as registers to set CLPOB, CLPDM, PBLK , etc.

    CCD Sensors OB and CLPDM.pdf
  • 0 in reply to Werner Metz
    Prodigy 20 points

    Thank you for the reply,

    I was thinking of the VSP01M02, I suppose, expecting a TG. I see that this needs a VSP1900 and CDCE913 or similar. It also seems that the VSP1900only supports color and interline b/w CCDs.

    Is there a 14/16 bit VSP01Mxx in the pipeline?

    As it turns out, the VSP01M02 may have good-enough bits, since the design is for low-light machine/inspection camera, and importantly, can be driven/programmed by simple processors with GPIOs. I'm looking at the reference block diagrams now.

    Ray

     

     

  • 0 in reply to Ray Schumacher
    TI__Expert 3370 points

    Correct, the VSP2566 will require an external timing generator and a vertical driver such as the VSP1900 to convert the CMOS level TG signals to the CCD drive voltages.

    BTW, the VSP1900 will support any CCD with up to eight vertical phases, color or BW, progressive or interline, etc. As long as the CCD does not require more than five (5) three-level signals and eight phases total, the VSP1900 should be able to support it. It is basically a level translator and doesn't care too much about the CCD architecture.

    All of the AFE's are programmed over a serial port for ease of use and to conserve system resources. The main difference is in how many registers each has and the specific definition of the register. They are often programmed using GPIO Ports, SDATA (Serial Data), SCLK (Serial CLock) and one device select for each device in the system sharing the SDATA and SCLK lines.

    Werner