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sample clock generation for ADC12D500RF (undersampling)

haertlms
Prodigy 100 points

Other Parts Discussed in Thread: ADC12D500RF, LMX2541, LMX2531

Hello,

I´ve got an ADC12D500RF adc and I want to undersample a signal at 2.2GHz. Therefor I need a sample clock with very low jitter (about 150fs according to the datasheet). I´ve already got a 32MHz clock and I want to generate 512MHz from this clock (according to the datasheet  it´s possible to use a higher sample rate than the 500Msps). With the help of the TI clock design tool I found the LMX2541SQ3740E. This was the PLL with the lowest jitter (about 200fs depending on the bandwidth). Is it reasonable to design a bandpass/lowpass after the PLL to filter the clock befor the adc-input and to maximize the slew-rate (this is both recommended here http://www.ti.com/general/docs/litabsmultiplefilelist.tsp?literatureNumber=slyt422)? Or do you recommend a completely other PLL?

And can you tell me whats the bandwidth of the adc-clock-input, so that I can better calculate the jitter from the phase noise.

Best regards

Markus

  • 0
    TI__Mastermind 44680 points

    Hi Markus

    The LMX2541 is about the best integrated PLL/VCO we have that can generate a 500 MHz clock. The LMX2531 has slightly better wideband phase noise, but this device is only available for higher clock frequencies.

    The clock input has a very high input bandwidth. For simplicity please assume it has a similar input bandwidth to that of the analog inputs.

    I hope this is helpful.

    Best regards,

    Jim B