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TSW30SH84EVM DATA_CLK

yunjiang shi
Intellectual 305 points

Other Parts Discussed in Thread: DAC34SH84, DAC3482, ADS4249

Hello,i have TSW30SH84EVM.By the user guide,when i use configer file DAC34SH84_1474p58MHz_2xINT_NCO_30MHz_single_sync_source_mode.txt,the FPGA_CLK1/2=1474.58/8=184.3225MHz.If the TSW1400 FPGA use FPGA_CLK1/2 to send data to DAC,the data rate A  is 184.3225MSPS,the data rate B/C/D are all 184.3225MSPS too.By the configer file,the DAC34SH84 is 2x interpolation,so the data rate A should be 1474.58/2=737.29MSPS,the DATA_CLK should be 737.29MHz.I can not understand what's wrong with me,please teach me,thanks.

  • 0
    Intellectual 305 points

     I have ads4249_dac3482_interfaces file.I find some code in FPGA_Top_Level.v.The tx_pll_output_clk rate and tx_pll_data_clk rate is same with lvds_tx_fpga_clk_p.

    If  lvds_tx_fpga_clk_p is 184.3225MHz,then tx_chA_sample[15:0] rate is 184.3225MSPS.

    Maybe you can send me a detailed verilog code sample to show me how to send data to DAC34SH84.

    Best reguards.

     

  • 0 in reply to yunjiang shi
    TI__Genius 17470 points

    Hi Yunjiang,

    The DAC3482 is very similar to the DAC34SH84, except that the DAC34SH84 has an extra data bus. So to add the extra data bus, you will need to modify the ALTDDIO_TX definition to include an additional 16 lanes. These lanes will need to be mapped to the appropriate FPGA pins. Everything else should be sufficient.

    Regards,
    Matt Guibord 

  • 0
    TI__Genius 17470 points

    Yunjiang,

    Regarding your first question, where are you measuring 184.32 MHz? For the TSW1400 firmware, the clock sent back to the FPGA will not match the data clock rate. To measure the data clock rate you will need to measure the clock at the DATACLK pins of the DAC.

    The code that you copied a picture of IS NOT from the TSW1400 firmware. The PLL In the TSW1400 FPGA multiplies the FPGA clock to generate the data clock. The example code does not do this, instead it just creates a copy of the FPGA clock. You cannot compare the clocks for the example code to the TSW1400 implementation.

    Regards,
    Matt Guibord

  • 0 in reply to Matt Guibord
    TI__Guru* 83015 points

    Yunjiang,

    The example configuration .txt file in the TSW308x GUI is designed to work for the TSW1400 GUI and default firmware. The reason why the FPGA clock is at 184.32MHz instead of 737.28MHz is because the DDR memory is being read in chunks of four samples at a time. Therefore, the FPGA clock rate had to be reduced by four in order to generate 737.28MSPS of data.

    -Kang

  • 0 in reply to Matt Guibord
    Intellectual 305 points

    Thanks for your kindly reply in time.

    Thanks matt Guibord,I know how to add the extra data bus now.

     

    Dear  ,I have another question.If the DAC34SH84 work clock is 737.28MHz ,then data rate A/B/C/D are all  737.28MSPS and DATA_CLK should be 737.29MHz.I don't know whether my understand is right or not.If DATA_CLK is really 737.29MHz,that means the FPGA clock can work up 737.29MHz,really?

     

  • 0 in reply to yunjiang shi
    TI__Guru* 83015 points

    Hi Yunjiang,

    I am assuming you are asking about the FPGA clock in terms of signal integrity perspective. I believe Matt and I have clarified that the firmware example on the FPGA app note is different than the default TSW1400 firmware. The FPGA app note firmware creates an example copy of the clock *from* the FPGA clcok *to* the DAC34SH84 DATACLK. This means in order to create a 737.28MHz of DATACLK, you will have to feed into the Altera FPGA with 737.28MHz of FPGACLK. 

    The FPGA_CLK send *from* the TSW30SH84 *to* the TSW1400 is in LVDS format, and will support the bandwidth needed for 737.28MHz of FPGA_CLOCK. 

    The FPGA_CLK traces are 100ohm differential line to support the 100ohm load termination within the Altera FPGA. This is the same format as the DAC34SH84 data line and DATACLK line with LVDS driver from the Altera FPGA and the on-chip 100ohm termination on the DAC34SH84. 

    Let me know if I misunderstood your question. 

    -Kang