Hi
I have 2 questions.
1) LM98620 Datasheet states 70MSPS 6 Channel. Does this 70MSPS throught mean each ADC throughput (70MSPS ADC x 3) or needs to be devided by 3 (23.3MSPS ADC x 3)?
2) Can it use single 70M Channel Rate if no two channels (only single channel) are used? or 35M Channel Rate is maximun speed?
Best regards,
Masa Katayama
Hello,
1) The 70MSPS is the maximum sampling rate of each of the three ADCs.
There are three main modes of operation for the LM98620:
1. 6 channel mode using ADC Rate MCLK – Clock Doubler is bypassed
2. 6 channel mode using Pixel Rate MCLK – Clock Doubler is used
3. 3 channel mode using Pixel Rate MCLK – Clock Doubler is bypassed
In 6 Channel Mode, there are two full cycles of ADCCLK for each sensor pixel period. This allows the two AFE channels to be multiplexed into the single ADC. In 3 Channel Mode, there is only one cycle of MCLK and ADCCLK per pixel period.
TXCLK (LVDS output clock) can be as high as 70MHz. Here is the LVDS output timing diagram showing the relationship between the TXCLK and the 10 bits of RGB sample for each pixel:
2) I believe the only other option is to use "3 channel mode using Pixel Rate MCLK" with this timing diagram and MCLK limited to 35Ms/s. Input sample rate is still limited to 35MSPS in the 3-channel mode:
Hope my responses have answered your questions?
Regards,
Hooman
Hello again,
One more thing:
Note that in the 3-channel mode, the TXCLK rate is the same as MCLK, and both are limited to 35Ms/s:
Regards,
Hooman
