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ADS5402 sampling, SFDR issues

Arvind Bhat
Prodigy 235 points
Other Parts Discussed in Thread: ADS5402

I am using the ADS5402 on a custom design card, which interfaces to an FPGA motherboard via high-speed mezzanine connector. I have verified that the ADS5402 works fine when test patterns are selected (via SPI programming). But i always see high spur content on the Ch-A digitized signal (terminating Ch-B into 50Ohm). When i sample Ch-B (terminating Ch-A into 50Ohm), the SFDR is quite close to the datasheet. I provide bandpass filtered, single-tone signals from 10MHz to 500 MHz with sampling rate set to 600MHz for both ADC inputs. When i provide the RF signals to both analog inputs (using a power splitter, and not terminating any analog input),  both channels exhibit worse SFDR (approximately 15dB higher than datasheet).

Somehow the Ch-A signal has bad SFDR and that leaks into Ch-B when i provide signals to both inputs. I have tried to isolate the problem by adjusting clock skews (i can provide fine skews to the 600MHz clock) to minimize timing errors. I have also tried a various spi configuration options. It is hard to say if it is a PCB layout issue, as we have done quite a few similar mezzanine cards (different data converters) with high success. Am i missing something with this ADC operation ? I will be happy share my code/ design files if that will help.

Regards,

AB

  • 0
    TI__Mastermind 29220 points

    Hi,

    Hmmm, I can't tell much yet with just a description.  May i see the plots that show the spurs?  And maybe the bit of your layout for the signal path for the two channels into the ADC?    Do you suspect a timing issue on the sample data into the FPGA?  My experience with that is that timing errors hurt SNR but do not show up as distinct spurs.  Do you have the option to make your single tone analog input 'coherent' with the clock and then instead of looking at the FFT of the data look at the time domain data for bad samples?  Our TSW1400 Capture Card has a feature in the time domain display of the data called 'unwrap waveform' that is very useful for seeing bad samples if the clock and input tone can be set coherent with a prime integer number of cycles of the input tone sampled by the sample clock.  There should be a picture of what an unwrapped waveform looks like in the User Guide for the TSW1400 or the User Guide for the TSW1200 on the TI web.

    I am not sure what putting delays in the 600MHz clock would do, if by that you mean delays to the sample clock to the EVM.  Delaying the phase of the sample clock would not affect timing of the sample data into the FPGA unless you are also using sample clock to latch data into the FPGA instead of the DDR bit clock from the ADC.  But from what you say, I wouldn't suspect timing issues on the sample data, but rather some coupling on the board.   Noise coupling into the supplies can also show up as spurs in the FFT. 

    Regards,

    Richard P.

  • 0 in reply to Richard Prentice
    Prodigy 235 points

    Richard,

    thanks for your response. I will work on sending you layout snapshots and coherent data plots. Is there an email address to send this ? I would prefer the layouts not to be in public domain.

    Attached are couple of data plots using 450MHz filtered input. Vref is 1.25V. The Ch-B plot SFDR is close to -65dBc.the problem is that i see higher spurs on Ch-A only. If this was a power supply noise, i should see this effect on Ch-B too i guess.

    With clock delay, i was trying to adjust the ADC input clock skew clock skew to have the input DDR clock sample the data at the center.

    Thanks,

    AB

  • 0 in reply to Arvind Bhat
    Prodigy 235 points

    Hello Richard,

    I am still having the spur issue with the ADS5402

    Thanks,

    AB

  • 0 in reply to Arvind Bhat
    TI__Mastermind 29220 points

    Hi,

    I sent my email address through the 'start a conversation' feature of this forum.

    I also set up an EVM on my bench with a 450M signal split and fed to both inputs of the ADC.  I set the sample rate a 560M since i did not have a filter available for the 580M that you had in your plots.  Please see attached.  I also set it up with both inputs set to 250M and sample rate 737M since I had those filters out for something else at the time.  I don't see what you see, so I think we need to look deeper into what you have set up.

    Regards,

    Richard P.

    ADS5402 both channels.zip