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Timing problem,,,,

sahit venkat
Intellectual 260 points
Other Parts Discussed in Thread: ADS5281

Here I have a question regarding ADS5281 .... 

here output of converter system clock , frame clock  (ADclk and Lclk)  and output data can we make dem in phase? yeah i have seen the data sheet it says we can program it in that way ..

But my question is if system(Lclk) clk and output data frame are in phase then if i interface a/d converter to fpga and i use system clk(Lclk) to latch the input data to IOB of fpga ..as clk and data are in phase dere would be certanily viloation of set up and hold time .......

  • 0
    TI__Expert 8895 points

    Hi,

    As datasheet of ADS5281 specifies, LCLK can be programmed while ADCLK and OUT are edge-aligned shown as Figure 2 in datasheet. So, FPGA can use LCLK as data synchronized clock by adjusting the delay option of FPGA. 

    Thanks,

    KW

  • 0 in reply to KW Nam
    Intellectual 260 points

    Thank you for ur reply ,

    I am interfacing ADC to fpga, we have ADclk and Lclk output from adc ,since I use (Lclk which is faster ) everywhere inside the fpga ..why do i require ADclk to inteface the fpga? I have minimum idea that ADclk gives the information that particular sample data has started ......

  • 0 in reply to sahit venkat
    TI__Mastermind 29220 points

    Hi,

    Yes.  Any time there is data that is sent out in a serial fashion one bit after another then there arises the problem of how to tell at the receiver which bit is the first bit of a sample and which bit is the last bit of a sample.   When the data is latched into the FPGA using the bit clock (LCLK) then the data must be converted from the serial stream of data back into a parallel bank of bits that are the sample.  There is no way to tell where to draw the boundary between the end of one sample and the beginning of the next sample on the serial data.

    Different data protocols deal with this problem in different ways, but the way the ADS528x solves the problem is to send an additional LVDS signal that identifies the boundary between samples, called the Frame Clock.  For the moment, forget that there is the word 'clock' in the name of the signal.  Think of the additional signal as a 9th data channel that just *happens* to have a data pattern that is known in advance.  That 9th data channel always carries the data 1 1 1 1 1 1 0 0 0 0 0 0. 

    So now if you want to know where the boundary is where one sample ends and the next sample starts, just look at that extra data channel and see where the 111111000000 starts.  Where that Frame Clock goes from the last 0 to the first 1 is the same place where the other 8 data channels start a new sample.  if you don't use the Frame Clock, you won't be able to know where to deserialize the data.

    Also take a look at the setup and hold timing specified in the data sheet between the bit clock (LCLK) and the other 9 LVDS signals.  The Frame Clock has the same timing as the other 8 data channels.  The bit clock can be used to latch the Frame Clock at the same time as it is used to latch the other 8 data channels.  This is how we use the frame clock in the FPGA on our TSW1200, TSW1400 and TSW1405.  The bit clock latches the frame clock just like any other data channel.

    Attached is a sketch of how the TSW1200 FPGA logic uses the Frame Clock to know where to deserialize the data.  The parallel bank of bits at the end hold a whole sample.  Every bit clock cycle the sample data is relatched into the parallel bank of bits.  Only on the one bit clock cycle where we see the frame clock pattern has gone from 0 to 1 do we use the mux to latch in a new set of bits from the shift-register flipflops that the serial data is streaming through.  This converts serial data to parallal data.  There is a Xilinx app note about using the ISERDES block instead, but that is not how we do it.  If you want to do it their way you would need support from them.  but you would still need to use the frame clock to know when to output parallel data from the ISERDES.

    Regards,

    Richard P.

  • 0 in reply to Richard Prentice
    Intellectual 260 points

    Thank you very much for your reply Richard,

    But i am not directly interfacing adc to fpga .....there is a kind of buffer where in b/w adc and fpga ..this buffer has maximum output skew of 400ps(0.4ns) so here alignment of adclk and data may be moved by tiny delay of 0.4ns..i am passing all data channels including lclk and adclk through that buffer is that ok ..can we do anything inside fpga to align them back..can we specify user constranits file to valid dem ....and ads5281 has aperture and variation is too less 20fs