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DAC5682Z Clock

Barry V
Intellectual 305 points

Other Parts Discussed in Thread: CDCM7005, DAC5682Z

On page 10 of the spec, note 3 says: "(3) Driving the clock input with a differential voltage lower than 1V will result in degraded performance." However:

1) There is nothing else in the data sheet saying HOW the performance is degraded.

2) The application section shows a CDCM7005 device driving the clock input and that device only has a 500mV minimum output (not 1V). A manufacturer who recommends a specific voltage level, doesn't explain the ramifications, and then doesn't abide by it in its own constraints is leaving this customer very confused.

Can someone explain to me what I REALLY need to do to properly use the DAC5682Z? I have successfully driven the clock in a previous application of this DAC using a Xilinx Virtex-5, but I'm anticipating a new design, and would like to get optimum performance.

Thanks, Barry 

  • 0
    TI__Genius 17470 points

    Hi Barry,

    Sorry the confusion. The noise performance will suffer when a lower clock amplitude is used. This will effect the wideband noise floor level, which will directly effect the ACLR performance.

    Regarding the CDCM7005, I think you're looking at the specification incorrectly. If you look at the definition of VOD in figure 9, you'll see that it's the difference between VOH and VOL. This is NOT the differential voltage. The differential voltage will be 2*VOD, because EACH output has a peak-to-peak voltage of VOD. So the minimum differential output voltage from the CDCM7005 is 1 Vpp differential. This meets the guideline.

    The DAC5682z will be "functional" with all clocks that meet the minimum 0.4 Vpp requirement. So I have no doubt that driving the DAC5682z with your Virtex-5 worked (LVDS output?). So, what was the result of the Virtex-5 clocking scheme? And how much improvement are you looking for?

    Here's a plot of DAC input clock level vs ACLR performance for a different part that is only 12-bits. You can see that performance starts to drop when the clock amplitude drops below 1 Vpp. Take this simply as an example.

    Regards,
    Matt Guibord 

  • 0 in reply to Matt Guibord
    Intellectual 305 points

    Thanks Matt,

    I guess my confusion comes from the fact that the CDCM7005 data sheet defines Vod as "Differential output voltage", so I assumed it meant it was the differential output voltage.  Silly me. :-)  Maybe if it had been specified as +/- 500mV...  Kind of a murky spec, but I've got it now.

    Thanks,

    Barry

    P.S. The Virtex-5 has an LVPECL output option; for some reason their newer chips did away with LVPECL.  I'm not looking for a specific amount of improvement, I'm just looking for the best I can get.

  • 0 in reply to Barry V
    TI__Genius 17470 points

    Hi Barry,

    I agree that the definition is a little confusing. I had to double check it a few times.

    One thing to be wary of regarding "FPGA clocks" is that their phase noise performance is likely going to be much worse than a dedicated clocking chip. This is due to the large amount of digital switching and the dedicated digital process.

    Regards,
    Matt Guibord 

  • 0 in reply to Matt Guibord
    Intellectual 305 points

    Agreed. But I've got one more concern: The maximum Vo of the CDCM7005 is VCC-.81==> 2.49 volts.  The ABSOLUTE maximum input for the DAC5682z CLKIN is CLKVDD+.5==>2.3v for a 1.8V CLKVDD.  That's a very real potential of overvoltage on the DAC input, isn't it?

    Well, I'm just going to use a 2.5V clock driver.