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ADS4149 "High Performance" Bits

Other Parts Discussed in Thread: ADS4149

Hello,

We are using the ADS4149, and can't find any information on what exactly happens in when we set the high-performance bits? 

We are seeing some bit errors, and the so we tried running without the high performance bits, and symptoms became worse.  We inject a fast edged pulse i.e. 800mV, 5us width and 5nS rise / fall time.  The high of the pulse is 0x2536 counts typical.  What we are seeing is that a random high bit will set resulting in a 0x2936.  The majority of the occurrences are that bit 10 sets just once in the stream and returns to valid data.  It can occur multiple times in a single stream of 10,000 samples.  We have seen two or three in a row in a stream of data, but this is not as frequent.  If we drop the amplitude of our pulse, the symptoms disappear.  We assumed it was an issue with the FPGA, but the "high performance" bits have us a little confused.

Thanks,

JC

 

  • I should have added a few more details...

    We are using the LVDS interface for data and clock with a 250 MHz frequency.  The ADC has a number of configuration settings related to LVDS voltages, we are running with the defaults.  Should those be tweaked, potentially?  We have been using the ADC’s ramp test mode to run ramps at the FPGA for over 6 months, so I we were fairly confident in the FPGA and its interface to the ADC. 

    Thanks again

  • Hi,

    HI PERF MODE 1: When set, clock buffer adds less noise, improving SNR a bit at higher input frequencies.

    HI PERF MODE 2: Disables some internal circuitry that improves distortion. This doesn't have any effect at high frequencies so it's recommended to turn it off for input frequencies higher than 230 MHz.

    Neither of these would likely effect what you're seeing. Can you provide the raw data that you're capturing? Also, a capture of the ramp pattern would be useful as well.

    Thanks,
    Matt Guibord