Other Parts Discussed in Thread: THS4121, CDCM61001, CDCE62005, LMK01000, CDCE72010, LMK03806, CDCP1803, LMK04806
Hi! I had defined to create a DAC to ADC but I may have to re-think the topology.
The real problem I have may be clock generation as distribution, I was planning to create the clock within the FPGA and them maybe buffered for DAC and ADC and later on up conversion.
But looking today at the issue of low level clock voltage I am being left of with different route to take, I could go back and forget about testing hardware and upgrade the FPGA part for better signal clock, or maybe create the clock circuit and then use it to clock the FPGA , ADC and DAC and up conversion.
Just amplified the clock output seen to be very messy, I search today for option like THS4121 and give some amplification and them buffer it but it seen to be adding circuit which I am not sure if its the right path.
I was thinking on Perhaps I could use something like "CDCM61001" for clock generation and then something like buffering for all the rest, and I could also take a 25 MHz signal out of the FPGA to create the distribution clock or simple use a 25 MHz oscillator to create all the clock.
Could you please give me advice what would it be the best topology taking into account delay and cost effective? Requirement narrow band, signal generation to about 5 to 15 Mhz up conversion .... them the downlink to getting the same bandwidth signal to base band level. Thanks
