TVP5151 SCLK

Tony,

Can you check the oscillator is actually oscillating correctly? Most if not all clock issues usually come down to incorrect crystal capacitors such that the oscillator is not oscillating.

Next, check that the TVP clock output enable is set in the TVP register map.

Finally, check that the OMAP pin muxing is not sourcing a signal to the clock input. (Best way to check this is to lift the clock output pin on the TVP so it is not connected to the board so that absolutely nothing else can drive it).

BR,

Steve

Steve,

OSC1 pin has 27M Hz classic sine wave with 1.8V peak to peak.  OSC2 pin has slightly skewed sine wave at 27 MHz with 1.8V peak to peak.

TVP clock output is enabled.

SCLK is 1.025 MHz square wave even when pin is lifted.  8 data pins appear to be switching at the same time as clock edges.

Tony

Can you please post your schematic, including power supplies, for the TVP part of your design along with the registers you set.

Can you check that all the supplies are at their correct level

I can't think of anything that would cause this behavior. There isn't much required to get the clock out.

Check that PDN is not active (should be high for normal operation) and check that a valid reset pulse has been presented to RESETB.

BR,

Steve

6354.Camera Interface.pdf

Supplies are at correct level.

PDN is high, RESETB is high.  I will have to check tomorrow on presence of reset pulse.

Register writes (non-default values):

Address 15h = 10h

Address 0Fh = 00h

Address 03h = 09h

Tony

The only thing I can see that might be an issue is that pin 27 should really have a pull down resistor. This does not always cause issues but sometimes can. (See figure 6-1, note I in the datasheet)

Do you have a TVP5151 EVM that you can compare against?

BR,

Steve

Below is a trace of PDN and RESET.

From the datasheet, it looks like that should be valid:

Cliff (working with Tony)

Cliff,

This looks fine.

Can you please try the following I2C sequence...?

0x7F = 0x00              // Restart CPU
0x28 = 0x00            // Auto-switch video standard
0x0F = 0x0A              // Select GPCL pin definition
0x03 = 0x6F              // GPCL high (not used), YUV output enable

BR,

Steve

Hi Steve,

I wrote the registers as requested:

CLIFF: ccdc_config_sync_if
CLIFF: data_size = 8
CLIFF: setting up ISP for bt656
cliff: tvp5150: writing 0x7f 0x00
cliff: tvp5150: writing 0x28 0x00
cliff: tvp5150: writing 0x0f 0x0a
cliff: tvp5150: writing 0x03 0x6f
0 (0) [-] 4294967295 898560 bytes 2342.793946 2342.794130 0.479 fps
cliff: tvp5150: writing 0x03 0x00
Captured 1 frames in 2.089631 seconds (0.478553 fps, 430008.777786 B/s).
8 buffers released.

The SCLK is still 1.XMHz during capture, so it does not look like much changed.

Thanks,

Cliff

Steve, 

Does the SCLK depend on the input video signal, or should SCLK run at the correct frequency, even with no video signal?

Thanks,

Cliff

Steve

Working w/ Tony & Cliff on this issue.  We ran a couple of tests here this AM.  First we drove the TVP5151 w/ a signal generator @ 12MHz and the SCLK pin measures 1.03MHz.  12MHz is the fastest our generator will run.  Next we ran the generator @ 1.2MHz and the SCLK measures 1.03MHz.  Next we ran the generator @ 600KHz, SCKL runs at 1.03MHz.  Finally we ran the generator at 1Hz and the SCLK still runs at 1.03MHz.

I see in the datasheet that the SCLK = 2 x Pixel Clock.  How is does the Pixel Clock relate to the crystal frequency?  Is this configurable?

Steve

Steve,

What happens if you stop the source clock after configuration?

What does the output clock look like before configuration?

Internally there is a PLL which generates an output clock by locking to the input video horizontal sync pulses. If there is no input video then the PLL free-wheels at approximately the nominal 2x pixel rate.

Have you checked all power supplies are correct and stable?

Have you tried replacing the device with another?

There really isn't much required to get the output clock wiggling, so it must be something simple that is wrong.

BR,

Steve

Steve,

How is the Pixel clock generated?

Steve

Nominally the horizontal sync period is measured and then used to calculate parameters for the internal PLL to give the correct number of clocks between output h-syncs. If there is no video input, or the input horizontal syncs appear to be outside some range then lost lock is indicated and a nominal 27MHz output clock is programmed in the PLL.

BR,

Steve

Steve,

All VDD voltage levels have been verified.

We are have this issue on ~3 different boards so it is not a single TVP5151 IC

We are planning to purchase a 5151EVM to help further troubleshoot this issue

Let me know if you can think of anything else - again, the SCLK is always at ~1MHz regardless of crystal frequency, camera signal vs. no camera signal...

Steve

I will try to re-produce this on the EVM since I can't think of anything at the moment that would cause this. It might be a day or so before I have any results/conclusions though, sorry.

BR,

Steve

Steve,

Problem solved for now.  We were driving the AVID/CLK_IN pin incorrectly with our micro.  We changed the micro pin to an input and now SCLK is driving a 27MHz clock.

Steve

Excellent. Glad you are up and running now :)

BR,

Steve