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ads1278 power up sequence - offset repeatability

Ian Mantle
Prodigy 80 points
Other Parts Discussed in Thread: ADS1278

I'm using the ads1278 and am sequencing the power supplies along with the analogue circuitry and the voltage reference.  At power on I collect offsets from each channel.  I then do a warm reset, which probably doesn't allow time for the analogue decouplers to empty, and I get a different set of offsets.

Is there a method I should use to get repeatable offsets from the device?  Should I be sequencing the Voltage ref?  Is there a procedure I should instigate after the supplies and voltage reference has stabilised?

Thanks

  • 0
    TI__Mastermind 43915 points

    Ian,

    I need a little more information to find a solution to your problem.

    First of all, how are you performing your ''warm'' reset? Are you cycling all of the power supplies off and on? If so, you do not want your reference voltage to be powered and supplying the ADC with a reference voltage while your converter is powered off. There is a recommended power supply order in the data sheet. Once you have all the supplies powered, you can apply the reference. Using this order you should not have any problems with the converter.

    You state that you are collecting offset codes from your converter and they are varying, how much are they varying from one power on cycle to the next?

    I can look over your schematic to see if I have any recommendations to improve performace if you would like. Feel free to post it in this forum or email me directly with the schematic at a-calabria@ti.com

     

    Regards,

    Tony Calabria

  • 0 in reply to Tony Calabria
    Prodigy 80 points

    Hi Tony

    The 'warm' reset involves cycling my power on reset circuitry which cycles the supplies to the adc.  This is a short duration reset and the various analogue supplies that are well decoupled around the adc probably don't discharge fully before the converter is up and running again.

    The offset variations are around 20mV but not on all channels.  This is noticeable after a cold start when the analogue circuitry may not have fully stabilised before we talk to the adc.  By performing a 'warm' reset the offsets seem to be more sensible.

    I have an FPGA which controls the interface to the adc in a consistent manner following the application of a reset so the only difference between the two resets are the various voltage levels on the analogue connections.

    Thanks

    Ian

  • 0 in reply to Ian Mantle
    TI__Mastermind 43915 points

    Have you disabled the reference voltage when you perform a 'warm' reset or do you leave the reference voltage powered?

    After the reset, verify that the CLK and SCLK are in phase and of a 1/1, 1/2, 1/4 etc ratio. We recommend keeping the SCLK and CLK in phase in order to minimize the noise. 

     

    Is there any way you can send me a schematic and some scope shots. Maybe then I can get a better idea of the problem.

    Regards,

    Tony Calabria

  • 0 in reply to Tony Calabria
    Prodigy 80 points

    Hi Tony

    I'm continuing to look through my ADC board, its slow progress.

    I noticed on the eval board that pin 7 is left unconnected but on the datasheet it recommends connection to DGND which I have on my board.  What is the function of this pin?

    Thanks

    Ian

  • 0 in reply to Ian Mantle
    TI__Mastermind 43915 points

    Ian,

    We recommend that you connect pin 7 to DGND on your board. In the latest version of our ADS1278EVM, Rev. D, we have connected pin 7 to DGND. In the ADS1278 early stages of development, pin 7 was used for a feature that was not implemented into the final design.  

     

    -Tony

  • 0 in reply to Tony Calabria
    Prodigy 80 points

    Hi Tony

    Can you check the revision code on my part please, it's 85A29YTG4.

    Thanks

    Ian

  • 0 in reply to Ian Mantle
    TI__Guru* 97655 points

    The revision code on your part has a date code from May of 2008. The last revision of the part was done well before it's introduction in June of 2007.

    Joseph Wu