ADS1243 is one of the performant TI devices that can be found easily from online store.
Unfortunately ADS1243 has no separate Vcc and Vdd power rail for analog and digital circuits and it requires a full-scale reference voltage that can reach the Vcc power rail only if Vcc is 5V. So, choosing to power the ADS1243 @ 5V for design costraints on full-scale reference, interfacing the ADC SPI to a MCU system powered at 3.3V becomes an issue.
SPI lines from MCU (3.3V) to ADC (5V) need to be boosted to at least 0.8 x Vdd = 4V to match ADS1243 V(Input high) logic level specs (datasheet page 2)
SPI lines from ADC (5V) to MCU (3.3V) need to be limited at 3.3V to avoid damages to MCU input ports
I tried different types of interfaces and I think the results I obtained could be useful for other forum users. Comments expecially on the last solution are very welcome!
1) specific application IC
The most rational solution I found is MAX3392E, a level shifter with 3 transmitters (-CS, SCK, MOSI) and one receiver (MISO). The chip is expensive (around 1.5$/1kpcs) and really hard-to-find for small (100pcs) production batches (is a non-stock for Digikey, Mouser and Farnell). Other cheaper and more common translators (74LVC2T45 for example) have too few transceivers and all in the same direction, so 3 units would be necessary to translate the full SPI bus.
2) transmission gate type level translators and diode limiters
I evaluated a solution using "homemade" 3V to 5Vshifters built around discrete p-MOS MGSF1N03LT1 and pull-ups (see Maxim app note APP 3007: Jul 21, 2004) and 5V to 3V resistor-diode limiters. The system works but the speed of the SPI bus cannot exceed 20-30kbs (due to the MOS capacitances I guess) even on the 3.3V side only, so having other SPI peripherals on the same bus requiring high data rate is not possible.
3) 74HCT + 74LVT buffers
I am going to build a cheap solution using easy-to-find parts: 74HCT125 (0.3$/100pcs) for translating -CS, SCL, MOSI and PWRDWN from 3.3V to 5V and a 74LVT125 (0.27$/100pcs) for translating MISO and -DRDY from 5V to 3.3V. One additional advantage is that connecting all the -OE (active low enables) of the used ports to the 3.3V -CS signal (and providing proper pull up for PWRDWN) the 3.3V SPI bus can be insulated from the additional length of the traces going to the ADC, thus improving the speed performances for other peripherals.
Comments and notes on your experiences are welcome!
Thanks
