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ADS1241 A/D Converter "Full Scale Resolution" Question

Other Parts Discussed in Thread: ADS1241

The ads1241 is a 24-bit A/D.  I am controlling the A/D with a uP via a SPI interface.

  I have having a problem figuring out the meaning of the "Full Scale Resolution" (FSR)  registers in the A/D.  The register is 24-bits long.  My Vcc voltage is 5V and Vref is 1.25V (Vref- is grounded).  What is the meaning of the FSR and can someone help with what values need to be written to these registers ?  BTW.  The highest voltage the A/D would see is approx 55mV, so I'm using a gain of 16 in the PGA.  Thanks

  • Actually, the "FSR" in this case refers to the name of the register(s): "Full Scale Register" - I tend to think of it more as "Full Scale Range". This application note describes how the offset and full scale registers work on a different series of converters, but the information is still applicable to the ADS1241. 

    If the app note doesn't completely answer your questions, come back here and we'll see if we can help further.

  • Thanks for your input.  It seems the FSR contains the inputs from your gain calibration.  I am getting pretty far along now; however, I am not quite getting the expected readings.  My setup is as follows:

    RANGE=0, PGA=32, Unipolar selected, ...my Vref is 1.235V (Vref- is grounded), Vcc=5V.  I am using the output from a potentiometer into the A/D to determine if the right voltage is
    measured (along with a voltmeter).  After doing the gain/offset cal according to the app note, my measurements do seem to work.  I get a larger value for a higher voltage.  However, I am not
    able to understand what the full-scale range is.  According to the data sheet, FSR = (2*Vref)/PGA, which should give 77.2mV.  However, I start to get all '1's in the A/D result when inputting a voltage
    voltage of >57mV.  If this helps, reading the FSR register after the cals gives a reading of 0xD68355 (14,058,325d).   Thanks.

     

  • Yes, the full-scale range of the converter is 2*Vref/PGA - the factor of two comes in because it is ±Vref (inputs are differential, so if you've set up, say, AIN0 to be the positive input and AIN1 to be the negative input, then AIN0 can go Vref above AIN1 - that would be positive FS; if AIN1 goes Vref above AIN0, then that's negative FS - note that if you're working single-ended, say, referenced to AINCOM and you have that tied to ground, then you can only exercise half the range of the converter).

    The UNIPOLAR bit doesn't make the input range unipolar - it only affects the output data code format. This is a frequent source of confusion on this part.

    So, in a gain of 32, the actual input range of the differential inputs (and you're always operating differentially - AINCOM is just another input to measure against) is ±38.6mV - if you're putting in 57mV, you're out of range, without doing any adjustments on the FSR registers. Does that make sense?

    I'll note here that using potentiometers is always a bad idea as a signal source to an ADC - their (likely) high impedance won't give you very accurate readings. If you have the input buffer turned on, that should help, but a low-impedance source is necessary without the input buffer.

  • Rick, thanks again for your inputs.  I tried wiring in a untiy gain op-amp between the potentiometer and A/D input, providing a low impedance signal.  That, together with enabling the A/D's
    internal buffer, provided good results.  One other questions, though, is how to interrogate the DRDY bit to determine when the calibration is complete.  According to the data sheet, the DRDY
    goes low when the cal is done.  However, when do you interrogate the register ?  If you read the register while the cal is taking place, I get 0xFF.  If I send the enable pin high (after entering
    the cal command), then bring enable on the A/D low (then enter the write/read command to interrogate the register for DRDY), I also get 0xFF.   If I wait a long time (i.e. allowing the cal
    to complete), I read 0xD0...which still doesn't make sense, since DRDY (bit 7) should be low.  Any suggestions ?

  • Hmmm... yes, that doesn't make sense. What does the /DRDY pin do while you're doing this? What should happen is during the cal, /DRDY is high, then drops low when cal is done - until, of course, the next conversion result is updated and /DRDY pulses high again (see Diagram 2). Could it be that you just happen to read the register when /DRDY has gone high again? That still doesn't explain the reading of the ACR register, though, because it doesn't agree with your other settings (i.e. having the internal buffer enabled).

    I wish you a Happy New Year, and hope this helps.