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SPI Clock Baudrate for ADS1148

RajaRao Malkari
Prodigy 110 points
Other Parts Discussed in Thread: ADS1148

Hi,

What is the range of SPI Clock Baudrate for ADS1148.

Regards

Raja

  • 0
    TI__Guru** 113765 points

    Hi Raja,

    The SCLK min/max clock period is shown on page 12 of the datasheet in the timing characteristics table.  The fastest is 2MHz and the slowest will be determined by the data rate selected.  The slowest SCLK frequency is the inverse of 64 times the data rate.

    Best regards,

    Bob B

  • 0 in reply to Bob Benjamin
    Prodigy 110 points

    Thank you Bob.

    In data sheet, on page no; 12, it is showing that 500 ns is the min SCLK and 64 Convertions is the max SCLK.

    So from my understand, 500ns (i.e 2M Hz) is the minimum. And what is the meaning of 64 Conversions?

    Regards

    ...Raja

     

  • 0 in reply to RajaRao Malkari
    TI__Guru** 113765 points

    Hi Raja,

    The minimum period is actually the maximum frequency.  2MHz is the fastest SCLK that can be used with the device.  The SPI will timeout after 64 conversions cycles, so the next clock must happen before the 64 conversion cycles have completed.  One conversion cycle is the period of time that it takes for the next conversion result to be ready.  If the data rate is set to 5sps, for example, one conversion takes place every 200ms. 64 conversions take 12.8 seconds.  64 conversions at 2000sps (period of 500us) is 32ms.

    Best regards,

    Bob B