Using the ADS1178 in a Data Logger Design

As per the design requirements of the system, sampling frequency is 16 KHz (16 KSPS). Hence the SYNC pin will be connected to a time pulse of 1/16 KHz (= 62.5 us).

We have the following queries in this regard. As per the design, we will set ADC in differential input mode, for eight channel simultaneous sampling, and FORMAT[2:0] = 001 (i.e. SPI with TDM in Fixed mode). Is this a feasible mode of operation?

Yes, you are able to run the ADC in SPI with TDM in fixed mode. It is important to make sure that your FCLK and SCLK are a fast enough to achieve your desired data rate of 16 KSPS. What is your FCLK? What is your SCLK? For best performance, we recommending limiting the fSCLK/fCLK to ratios of 1, 1/2, 1/4, 1/8, etc. Figure 18 shows that it will take 132 SCLK cycles in order for all of the data to be output, so make sure that your SCLK is set appropriately. 

As the SYNC signal allows for the conversion to be aligned with an external event, we will get samples at every 62.5 us, for all eight channels. Is our understanding correct?

Figure 14 shows the relationship between the /SYNC signal and the FSYNC signal. If you want to have a date rate of 62.5 us then you need to make sure that the frequency of your master clock and SCLK are fast enough to convert and read out the data in TDM mode in 62.5 us. (1/fSCLK) * 132 <= 62.5 us.

As per our understanding, the SYNC signal should work as start of conversion (SOC) for the ADC. Hence the ADC shall sample at the frequency on SYNC signal. Is our understanding correct?

Use Figure 14 as a reference. As you pulse the /SYNC low you must also trigger the FSYNC immediately following. Make sure FSYNC is a free running clock. You must wait 127-128 conversions after FSYNC pulses for the new data to be ready. As the data is output in TDM mode the next conversion cycle can begins. The /SYNC can be looked at as the start of conversion for the ADC. It does not set the sampling frequency or data rate.

If answer to the above point is yes, then it means we can dynamically vary the ADC sampling frequency by changing the frequency of the SYNC signal. Is our understanding correct? Please confirm.

/SYNC controls when the conversion starts. Once /SYNC is pulsed, you must wait 127 - 128 conversion cycles to gaurantee that the data is ready. The sampling frequency is set depending on your choice for your master clock (fclk), and your modulator setting. The data rate is controlled by the CLKDIV bit and what you choose for the fclk frequency (see table 4).

Make sure that your SCLK speed is fast enough for your data rate in TDM mode. Remember it takes 132 SCLK periods for the data to be output in TDM mode.

We presume that the settling time refers to the time taken by the ADC output to change with respect to a step change at the ADC input. Is our understanding correct?

The time it takes for the ADC output to change with respect to an input step change is the group delay. The settling time incorporates the group delay and the time for the data to settle. See figure 6 on page 11 for a diagram.

In earlier query concerns are raised on the group delay and settling time of ADS1178. How does group delay and settling time impact the sampling frequency? Please clarify.

Group delay and settling time are expressed in terms of conversions. As you change the conversion time (by modifying fclk, etc.), the group delay and settling time will change. If you plan to use a 16KSPS data rate, then you will need to wait 128 conversions for your first set of data to be ready. (1/fdata) * 128 = 8ms. This takes into accound the group delay/settling time and any other time that the modulator needs.