My research group purchased two ADS6445EVM and HSMC-ADC Bridges for use with Terasic DE-4 development board. We received Rev A. HSMC-ADC Bridges. While the documentation link on the website says the documents are for Rev A., the actual documents are for Rev B. It seems that Rev. A routes the ADC frame clock to the CLKIN_p1/n1 differential pair rather than the TX_p16/n16 pair as in Rev B. Since the clock pin does not have a deserializer, this makes it impossible for us to deserialize the frame clock and perform pattern checking to properly align the data. How can we resolve this issue.