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Corrupted data after powering up ADS1274

James Cammack
Prodigy 30 points

Other Parts Discussed in Thread: OPA1632, ADS1274, ADS1271, LM337, LM317, ADS1278, PCA9535

I have a ADS1274EVM early version(OPA1632's). Serial data (SPI mode)converted to byte parallel format by CPLD sent to Cypress FX2LP USB2.0  FIFO into PC. I have two prototypes call them "System 1" and "System2".  "System 1" has high quality analog linear power supplies with digital supply coming from USB bus power.  Power sequence for "System 1" plug in USB cable 3.3 volt  regulator on FX2 board powers FX2 ,3.3 volt powers ADS1274EVM I/O with your on-board 1.8 volt regulator powers ADS1274 core, switch on analog supplies. No problems all four modes work up to 27 MHZ clock speed SCLK =1/2 CLK.

"System 2" all power, analog and digital from sequenced linear power supplies. Power sequence for "System 2" lift jumper J13 on EVM(disable on-board 1.8v reg.) apply 1.8 volts to core, wait ~ 2 seconds a apply 5 volts to 3.3 reg. on FX2 board and EVM I/O wait ~ 2 seconds apply analog power.  "System 2" has corrupted data sometimes after power up, and sometimes it's OK after power up.  Is there a way to reset the ADS1274 after power up?  If it starts up clean it runs 100% like "System 1". It seems like I have a ground bounce or glich in the supplies at start up which I can not find. Both systems use same hardware and software except for the power supplies. I flush the FIFO's and apply SYNC NOT before start of each acquisition.  "System 1" uses LM317 and LM337 regulators. "System 2" uses LM78XX and LM79XX regulators. One poor solution to problem is to turn "System"2 on and off until I get a "clean reset" on ADS1274. The CLK is active at power up.  If I enabled CLK after power up would I get a reset.  Is the ADS1274 similar to the ADS1271 in that if you power down(PDWN not) all the channels for 2^19 clock cycles and then re-enable the channels you get a reset condition? Attached data files of  problem. Thanks Jim.

7217.Clean Start up.doc

0537.Corrupted startup.doc

4861.Clean startup no Signal.doc

3441.Corrupted startup no Signal.doc

  • 0
    TI__Mastermind 23235 points

    Mr Cammack -

    Where are you taking the DOUT signal from?  With this device, we put in some logic to align the data with the SCLK output for higher frequency operation in FS mode.  You may want to try taking the data from the J2 header which is before the logic (flip-flop U20).

    You might want to also try powering down all the channels once all the supplies are up and then back on to see if this helps to resolve the behavior you are seeing.

  • 0 in reply to Greg Hupp
    Prodigy 30 points

    Thank you Greg for your response . I am already getting the serial output from header J2 DOUT1.  I cut the SCL(I^2C) trace on the EVM because your I^2C I/O expander (U17,PCA9535) has an address of zero which is the same address as my FX2 I^2C firmware ROM.  So I can not programmatically power down all the channels. However I did put all channel on dip switch S10 low for a few seconds with CLK at 1.048X10^6 Hz and then back high to see if is would give me a reset “it did not”.  I will change U17’s address to something other than zero so as not to conflict with FX2’s firmware ROM to do it via software just in case the switch’s  have switch bounce. I’m still not clear about “Global POWER –ON RESET”.  On page 35 of your (PDF data sheet for ADS1274/ADS1278 ) under POWER SUPPLIES.  It seems to imply that the chip only gets initialized at power up. Is this true?  Also it states “proper ramp rate for supplies” but does not define it.  Also “the power supplies should be applied before any analog or digital pin is driven”.  The diagram on bottom of page 35 shows “Internal Reset” at AVDD threshold. Is the CLK internal to chip enabled at this point?  I have clock enabled externally at power up. I have tried power sequences per figure 84 and IOVDD and DVDD tied together follow by AVDD with intermittent success(sometimes clean sometimes dirty). I have looked at analog signals at input pins on ADC and 2.5 volt reference at reference pins on ADC and all are clean while showing dirty on digital domain side. Also checked that I have a “Star” ground point at ADC ground plain. Next will try to change power circuit to FX2 broad.  FX2 is powering up and booting up at same time as ADS1274. Make ADS1274 power up before USB and CPLD. Also try soft start on power supplies.  Thanks Jim 

  • 0 in reply to James Cammack
    Prodigy 30 points

    Problem solved.  Found that if I use USB bus power to power up ADS1274 core and I/O together and then apply analog power to ADS1274 approximately 0.2 seconds after USB bus power(using RC time delay circuit) I get consistent clean “Global Power-on Reset”.  When FX2 starts up from EEPROM it puts its 8051 CPU in reset while serial engine logic loads firmware into RAM and then releases the CPU which starts to configure its I/O pins and drive I/O pins on my CPLD which in turn can cause activity on ADS1274 pins. I do not have logic analyzer but assume that the time to put CPU in reset, load ROM and release CPU  something greater than about 0.2 seconds is why it works. Anyway that’s my theory but it works. Attached images of quality of signal conversion. Thanks for Help Greg Jim