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ADC ADS8320 conversion doesn't behave as expected. Adaptation required?

dsb
Prodigy 30 points

I've designed a Galvanostat (meassures the voltage drop vs time in a sample while applying a constant current) and the final ADC conversion shows some extrange behaviour. Instead of showing a continous variation in the voltage meassured, it show a plateau-like conversion. Meaning, the conversion is constant for a few samples, forming a plateau and providing the exact same 16bits value, and then jumps to the next voltage value. This behaviour is more visible as the rate of change in voltage lowers.

The experiment was carried with a 100ms sample rate, but my software can change that value to whichever I want. The conversion is made with the full 16bits allowed by the IC. The voltage value shown in the graphs is the voltage drop in the sample, which is the value given by the ADC after some tranformations (an offset and a gain). The plateaus form at exact 10mV jumps and that is, in DAC values, an exact 64. That value is a power of 2, so it's too much of a coincidence, isn't it?. I can show you an excel sheet with the saved data from several experiments, and the same exact DAC value (with +-1 variations) is read several times in a row. It's impossible that the signal is so stable that a 16bits DAC reads the same value 4, 5 or even 6 times in a row or show only a 1 or 2 bits difference in 10 consecutive meassurements.

I tried changing the ICs in the circuit, changing the experiment conditions and many other things, but the problem seems to be in the way the ADC reads the data.

I was using a multimeter to read the in voltage and, strangely enough, while the multimeter was connected, this behaviour disappeared and the conversion went as expected, but a bit of noise was added. I suppose that the multimeter pressence stabilized somehow the ADC reading, but i wasn't able to recreate it on my own.

Here are some images of my circuit and the curves I got from different  same-conditions experiments. The one in black is meassured with the multimeter connected. It is of note than the other three show the exact same plateaus at the same voltage values. I'm only showing the last past of the signal path, which I think is the only part relevant for my question.

Can anyone please give me a hint of what may be happening?

  • 0
    TI__Prodigy 10 points

    D'maso,

    One visible source of error is the impedance mismatch on +IN and -IN of ADC. At the low sampling rate you mention (10 Samples per second) the ADC sampling circuit could introduce nonlinearity only right at the sampling instant.

    Adding the digital multimeter across +IN and -IN might be introducing bypass capacitors and reducing the amount of impedance mismatch.

    Impedance matching can be achieved by adding 5kOhms from -IN to ground, with additional dummy diodes to ground and 5V supply from -IN.

  • 0 in reply to Yujendra Mitikiri
    TI__Guru 55466 points

    Hello D'maso,

    The source of the analog input voltage must be able to charge the 45pF sampling capacitor within the required acquisition time. 

    In the post above, you have mentioned  a 100ms sampling rate is used.   The allowed acquisition time is 4.5 DCLK cycles. Depending on the allowed acquisition time, the 5kOhm resistor at the output of the OPA may not allow the 45pF to fully settle to the target value during the acquisition time; resulting in conversions that are not accurate.  What is the DCLK frequency currently used in the set up?  Typically an RC filter is placed at the input of the SAR ADC, and the resistor and capacitor values are chosen so they settle within the acquisition time. 

    Best Regards,

    Luis 

  • 0 in reply to Luis Chioye
    Prodigy 30 points

    Thanks Yujendra and Luis for your suggestions. I didn't explain myself correctly when I stated that the samplig rate was 100ms. That should be the software sampling rate. At the hardware layer, the firmware spends the last 30% of those 100ms performing continous meassurements and averaging them at the end of the sampling time.

    I'm using a 32MHz PIC and the DCLK is about 1 - 1.1MHz (firmware dependent). I used this same configuration in other circuits and found no problems with the results obtained with it. Including the firmware overhead between meassurements, the real sampling rate should be around 30.7us or 33KHz.

    Yujendra, I tried removing the resistor and the diodes (they are there only for over-under voltage protection of the ADC) and the problem still occurs.

  • 0 in reply to dsb
    TI__Prodigy 10 points

    D'maso,

    You might want to read the discussion in the link below on the forum for possible causes to the plateau you are seeing. I suspect that you might have similar problems.

    http://e2e.ti.com/support/data_converters/precision_data_converters/f/73/t/190725.aspx

    You could try increasing C15 to 1 uF.

    Best Regards,

    Janakiraman.