• State Resolved
  • Locked Locked
  • Replies 5 replies
  • Subscribers 48 subscribers
  • Views 891 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS1242 problem

Roman13554
Prodigy 30 points
Other Parts Discussed in Thread: ADS1242

Hi

We used ADS1242 in our thermocouple measuring device.

ADC registers:

SETUP=0x03; MUX=0x01; ACR=0x16; other registers in default state.

f osc = 2.4576 MHz

As you see, we don't use ^DRDY pin. Therefore we couldn't syncronize data readings with ^DRDY falling edges.

How could we start an ADC conversion to predict the moment of conversion finishing?

We tryed to do this in the following way:

1. Send DSYNC command.

2. Send RDATA command, read incorrect data.

3. Wait 280 ms.

4. Send RDATA command, read valid data.

We faced the following problem: After items (1) and (2), first ^DRDY falling edge comes after 133.3 ms instead of expected 266.6 ms.

  • 0
    TI__Guru**** 180931 points

    Hi Roman,

    Have you been able to verify that the SETUP, MUX and ACR registers are set to the correct values using the RREG command?  After your configuration sequence, if you simply let the ADS1242 free run, what rate do you see the DRDY signal coming out at?

    Sending RDATA after DSYNC should not upset the modulator timing - did you have the 4*tosc period delay between 1 and 2 above (see page 6 of the datasheet)?

  • 0 in reply to Tom Hendrick
    Prodigy 30 points

    Hi Tom,

    Yes, i have. SETUP, MUX and ACR is correct.

     

     

    I did the following:

    1. RESET command

    2. write SETUP=0x03, MUX=0x10, ACR=0x16, all other regs are in default.

    3. DSYNC command

    4. RDATA command, they read previous result and don't use it.

    5. 720ms delay

    6. RDATA command to read real result

    7. Then go to point 3.

    And they see next picture on oscilloscope

    A - /DRDY signal

    B - SCLK signal

    t_1 = 133.3 ms ( 7.5Hz)

    t_2 = 266.6 ms ( 3.75Hz)

    (1) - exchange with ADC (see p.4 & 5 (DSYNC É RDATA)

    (2) - exchange with ADC (see p.6 (RDATA) to get valid data.

    The question is: If DSYNC starts new conversion, why t_1 is 133ms, not 266?


  • 0 in reply to Roman13554
    TI__Guru**** 180931 points

    Hi Roman,

    Are you working with Alexander on this?  One of my associates is working this very same issue at the moment and we hope to have resolution shortly.

  • 0 in reply to Tom Hendrick
    Prodigy 30 points

    Yes, i working with Alexander from Saint-Petersburg departament. He suggested to take the second DRDY after first data. It is not solution for us.

  • 0 in reply to Roman13554
    TI__Guru* 97595 points

    I've mentioned this to Alexander already, and I think you have the information already, but I'm posting this here to be complete.

    I've assembled this circuit using an EVM and tested out the results and it looks like the early /DRDY pulse is occurring in this case.

    In the default case, the part runs at 15Hz, with a data period of 66.6ms. After the DSYNC command, the next falling edge of the /DRDY line occurs correctly at 66.6ms.

    In the other data rates however, the /DRDY comes in exactly half the time as expected. In the 7.5Hz mode (or 133.3ms data period) and 3.75Hz mode (266.6ms data period), the first falling edge of /DRDY comes in exaclty hald the time (in 66.6ms and 133.3ms respectively).

    However, once past this first data read, the data rate resumes at the programmed value.

    Joseph Wu