I have been using a TI DAC 3283 with a DACCLK of 250 MHz and a 2X interpolation to generate an IF output of 70MHz. I have a power up sequence and use the Frame signal once after all the SPI controls have been setup to synchronize the DACCLK and the DATACLK. This design has been working well for over 2 years.
Now I am creating a new design that required a 500MHz DACCLK with 4X interpolation to create a 140MHz output.
I enable the second interpolating FIR in CONFIG1 (set it to 0x31). This all works, but only 50% of the time. The other 50% of the time, I have a bad output spectrum. If I write 0x21 to CONFIG1 and then 0x31 (to disable and then re-enable the 4X interpolation), there is a 50/50 chance that the output will correct itself. Re-issuing the frame signal to re-synch the system does not correct the problem.
Other than the bad output spectrum I don't have any other indications that there is anything wrong.
Do you have any suggestions on how I might properly initialize the chip for this mode? I am writing the registers starting with register 1 to register 1F (SPI is controlled from an FPGA - which incidentally also sets up the PLL chip that selects the DACCLK - DATACLK is derived from DACCLK to be 1/4 DACCLK). I did notice that writing the SPI registers in different orders can make a difference.
Any help would be appreciated.
Urs
