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AFE7225 SPI Programming

Jeff Battin1
Prodigy 50 points
Other Parts Discussed in Thread: AFE7225

The AFE7225 SPI uses a 20-bit serial register. My SPI controller only handles multiples of 8 bits (bytes). Do I have to bit bang or can the AFE handle padding of 4 bits on the end a config register command before de-asserting SEN? Can I format the command to the AFE to handle message of 24 clocked bits (pre or post padding)?

  • 0
    TI__Expert 8895 points

    Hi,

    You can send 5 bytes at a time (40 bits) with SEN active and SCLK and configure two registers at a time. This should resolve the issue of 20 bit AFE722x register and 24 bit data from the external controller.

    During this entire 40 bit width, please keep the SEN active (LOW) and AFE722x will configure the first two registers. If you have to configure more registers, always configure the registers in multiples of 2 for solving the issue of 20 bit / 24 bit.


    Another option is to set SEN high after 20 cycles of SCLK, andthe remaining 4 SCLK will be ignored. Whenever SEN goes high, the SPI state machine gets reset and all subsequent pulsed on SCLK are ignored. But it will be required to meet timing from SCLK and SEN. Setup time between SEN falling to SCLK rising edge & hold time between SCLK rising edge to SEN rising have to be minimum 50ns. It depends on your SCLK speed.

    I think first option above looks easy for you.

    Thanks,

    KW

  • 0 in reply to KW Nam
    Prodigy 50 points

    Thanks KW,

    I implemented your suggestions (just sending command 2x) a I still can not seem to access the device verified by reading a register.

    Checked SEN = active low and timing

    Steps:

    WRITE CONFIG107 -  2 -SOFTWARE RESET

    WRITE CONFIG111 - 2  - Set WHAT_IS_SDOUT to Digital o/p

    READ CONFIG111 - check if = 2

    Here is my trace:

    m:s.ms.us Dur Len Record Data
    0:00.000.000 Capture started [10/30/13 15:08:43]
    0:15.233.648 19.100 us 5 B Transaction 0000 0000 2000 0000 0200
    0:15.233.648 19.100 us 5 B    MOSI 00 00 20 00 02
    0:15.233.648 19.100 us 5 B    MISO 00 00 00 00 00
    0:18.163.320 18.750 us 5 B Transaction 2000 A000 2200 0A00 0200
    0:18.163.320 18.750 us 5 B    MOSI 20 A0 22 0A 02
    0:18.163.320 18.750 us 5 B    MISO 00 00 00 00 00
    0:20.838.019 18.850 us 5 B Transaction 2000 0000 1200 0000 0100
    0:20.838.019 18.850 us 5 B    MOSI 20 00 12 00 01
    0:20.838.019 18.850 us 5 B    MISO 00 00 00 00 00
    0:20.838.039 18.600 us 5 B Transaction 2000 A000 0200 0A00 0000
    0:20.838.039 18.600 us 5 B    MOSI 20 A0 02 0A 00
    0:20.838.039 18.600 us 5 B    MISO 00 00 00 00 00
    0:22.975.641 18.800 us 5 B Transaction 1000 0000 1100 0000 0100
    0:22.975.641 18.800 us 5 B    MOSI 10 00 11 00 01
    0:22.975.641 18.800 us 5 B    MISO 00 00 00 00 00
    0:22.975.661 18.650 us 5 B Transaction 1000 4000 0100 0400 0000
    0:22.975.661 18.650 us 5 B    MOSI 10 40 01 04 00
    0:22.975.661 18.650 us 5 B    MISO 00 00 00 00 00
    1:40.662.873 Capture stopped [10/30/13 15:10:24]

    Any other suggestions?

    JB

  • 0 in reply to Jeff Battin1
    TI__Expert 8895 points

    Hi,

    Please refer to the page 19 of datasheet. "A11:A8,00000000,00000001" has to be written for readout after configuring SDOUT as a digital output pin. "A11:A8" is the page address. If you want to read CONFIG111, the page address is 0x2 (0010). And then,  write the address of the register to be readout as Figure 4-2 in datasheet.

    Thanks,

    KW

  • 0 in reply to KW Nam
    Prodigy 50 points

    Hi KW,

    Thanks for your response. I believe I am following the data sheet, did I miss something? If the following looks ok, I will do another deep drive into the hardware.

    Contained in the above trace:

    MOSI (00 00 2) - Config107 - page 0 - addr 00 - data 02 (software reset)

    MOSI (20 A0 2) - Config111 - page 2 - addr 0A - data 02 (SDOUT = Digital o/p)

    MOSI (20 00 1)  - Config111 - page 2 - addr 00 - data 01 (set read mode for page 2)

    MOSI (20 A0 0) - Config111 - page 2 - addr 0A - data XX (MISO should return data)

    UPDATE: Hardware timing and signals look good as per data sheet.......

    Thanks,

    JB

  • 0 in reply to Jeff Battin1
    TI__Expert 8895 points

    Hi,

    The readout procedure looks ok. I'll check this with designer and come back to you. By the way, what is the SPI frequency?

    Thanks,

    KW

  • 0 in reply to KW Nam
    Prodigy 50 points

    Thanks KW,

    tried it at 25 MHz and then at 1.25 MHz.

    JB

  • 0 in reply to Jeff Battin1
    Prodigy 50 points

    Thanks KW,

    Now programing the AFE correctly, it was a combination of the register settings and a debug hardware problem.

    FYI, padding a nibble at the end of the 20 bit register also works.