Other Parts Discussed in Thread: LM98714
Hi members
This is Ben, from JAPAN.
Please support LM98714's two question.
No1: How much is min-range INCLK? exampl : 1kHz is OK?
No2: Engineer uses INCLK is 5.0992MHz.
If changing to uses INCLK 4.8MHz for 5.0992MHz
that how long to delay of sampling(ns) ?
Best regard.
BEN
Hello Ben,
To answer your questions: adf
1. For the LM98714, the minimum INCLK is specified here as 5MHz (within the full LM98714 datasheet which is available if we have an NDA in place- you may contact your sale representative for this):
The low limit for INCLK=PIXCLK mode is also 5 MHz (even though it is not explicitly stated in the table).
Below this frequency, the circuitry creating the bit times in the LVDS output stream gets worse. So the bits that are too wide or too narrow tend to get worse and worse as the frequency drops.
2. When changing the frequency of INCLK, the internal PLL requires some time to re-stabilize before accessing SPI or guaranteed operation/performance.
For moderate changes a delay of 1ms should be long enough for the PLL to re-lock. They may need to add a little additional time for the LVDS receiving IC PLL to stabilize as well.
When powering up the device we recommend 100ms for the PLL to lock and the POR reset circuitry to clear.
Regards,
Hooman
