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DAC5681Z - CLKIN status during SIF registers programing

Benjamin KOSICKI
Prodigy 130 points

Other Parts Discussed in Thread: DAC5681Z

Hello,

Currently, we are working on a RF system tester with a DAC5681Z piloted by a FPGA (For LVDS data) and configured by a STM32 (for programing the internal registers).

We wish know if a risk of DAC malfunction is possible if the CLKIN is absent during the programing of SIF registers.

By advance thank you,

BR.

  • 0
    TI__Genius 17480 points

    Hi Benjamin,

    Although writing to the actual registers shouldn't pose a problem, the startup procedure will be violated. I'll need to try this on the bench to see if there are any specific caveats that prevent this. In general, we will not guarantee correct functionality if the startup procedure is not followed.

    Regards,
    Matt Guibord 

  • 0 in reply to Matt Guibord
    Prodigy 130 points

    Hi Matt,

    Thanks you for your reply, we have made a powering up procedure for our design.

    On the same subject concerning the CLKIN : 

     - Do we have an  obligation to respect a synchronization (rising and falling edge) between CLKIN and DCLK ?

     - The datasheet specify a duty cycle of 50% (typ) but not the min/max acceptable for the DAC. The DAC can he work with a duty cycle set to 60% ?

    Regards,

    Benjamin Kosicki

  • 0 in reply to Benjamin KOSICKI
    TI__Genius 17480 points

    Hi Benjamin,

    You do not need to guarantee timing between CLKIN and DCLK because an internal FIFO will absorb any skew. However, they both need to come from the same time base.

    I would expect this to be fine. What clock source are you using? Most high quality clock sources are better than +/- 10% duty cycle.

    Regards,
    Matt Guibord