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ADC for undersampling

Cato
Prodigy 40 points
Other Parts Discussed in Thread: CDCE62005, CDCM7005, ADS54RF63, ADS5400, ADS5463, ADS5474, CDCE72010

Greetings,

 

I am trying to learn some things about software defined radio (SDR), so I figured i would start a hobby project to introduce myself to the topic. 

I have some DSP under my belt, though not a great deal.  I want to undersample (or band-pass sample, or whatever you want to call it)  RF signals, like AM/FM Radio, and demodulate them.  I already own an XUP-VP2 (virtex 2 pro) FPGA board that I want to use, and i would like to find a ADC development board that I can connect, to do various SDR projects. 

my problem is:

if I do direct undersampling of the band-limited RF signal, I don't have the luxury of a mixer on the front end to put the information at a nice IF.  therefore, if I want to tune my SDR to different frequencies (say go from AM to FM band), I would have to change my sampling rate to avoid aliasing.

My questions are:

1) are there any ADC development boards out there with adjustable sampling rates?

2) if I have to supply a clock to the ADC board, what is the best way to do it? (I am worried that a VCO or a clock from the FPGA would have a lot of jitter, and thus reduce my ability to demodulate the information.

 

I was looking at the AD9219-65EBZ development board, but am not sure how to adjust the sampling rate without introducing jitter/noise.

 

any help would be great,

-Cato

  • 0
    TI__Mastermind 18095 points

    First of all, I applaude you on getting involved in this very interesting topic. 

    1) are there any ADC development boards out there with adjustable sampling rates?

    Yes, the portfolio of TI ADC devices operate over a range of sampling rates up to their published maximum specifications.  For you application with RF signals up to a 100 MHz or so, it may not be needed to undersample.  There are a number of high sampling rate ADCs that can capture the entire bandwidth that you are intereested in and then filter and demodulate in the digital domain. This is generally the approach for a SDR since it is much easire to modify filters and such in the digital domain that in the analog domain.

    2) if I have to supply a clock to the ADC board, what is the best way to do it? (I am worried that a VCO or a clock from the FPGA would have a lot of jitter, and thus reduce my ability to demodulate the information.

    The clock is a tricky situation.  A clock from the FPGA will have a lot of jitter and not useful for the ADC.  A VCO clock may not be much better.  A typical fixed freqeuncy clock solution that is typically used is the CDCM7005 Clock distribution chip with a VCXO.  The CDCM7005 with synchronize the VCXO to an arbitrary reference and provide ouptuts at multiples of the VCXO frequency.  This approach provides  low jitter clock source but only a fixed set of frequencies.  With clever use of frequency selection and divider ratios it may be possible to utilize that device for your requirements if a variable clcok frequency is needed.  An alternative is to use a CDCE62005 which provides a variable frequency output, but the phase noise is not well suited for ADC applications.

  • 0 in reply to RJ Hopper
    Prodigy 40 points

    thanks for the information.

    after doing a lot of research in the last couple weeks, I have decided that I want to undersample in the range of 1GHZ.  I was planning on doing broacast AM/FM before jumping into the high frequency stuff, but I have gone back on that decision.  does TI have any ADCs with a full-power bandwidth in the 1ghz range?  it has been difficult to find such an ADC, especially since that is not a commonly specified rating for ADCs (so I can't filter on it in digikey, mouser, ect).  I found one from National Semi (sorry I keep naming non-TI parts on the TI forum :P ).

    do you think the jitter/phase noise on a clock distribution chip would be acceptable at 900mhz RF, with a sampling rate from 80 to 100mhz?  I may be able to get away with a sampling rate as low as 45mhz, but I am not sure yet.  also, do you think that there are any clock dividers/multipliers capable of low enough jitter/phase noise to sample at that rate?

    I guess the primary question is, how do I quantify the affect of jitter/phase noise on my SNR?  are there any standard methods for doing so?  I can't seem to find much on the net.

    also, how does one deal with a quadrature signal in the digital domain?  should I split every other sample, so I affectivly cut my sampling rate in half but have two "phases"?

     

    Thanks, Cato

  • 0 in reply to Cato
    TI__Expert 3865 points

    Cato,

    currently we have 3 ADCs available that would allow you to undersample a signal above 1 GHz. You can take a look at the ADS5463 (ADS54RF63 has an optimized RF front end giving excellent performance >1GHz), ADS5474 and ADS5400. Here is a quick summary:

    ADS54(RF)63: 12bit, 500Msps

    ADS5474: 14bit, 400Msps

    ADS5400: 12bit, 1Gsps

    We don't show a minimum sampling rate in the data sheet but there is a 3D SNR/SFDR graph in the data sheet showing performance down to 170Msps. I've tested the ADS54RF63 down at 100Msps yesterday but below that we can't give any guarantees.

    In terms of phase noise and jitter, it depends what SNR you are trying to achieve. The ADS54RF63 has internal aperture jitter of ~150fs. In order to obtain an SNR of ~60dB at 1GHz input, the clock jitter needs to be ~100fs which is very tough to accomplish. We typically look at the CDCE72010 or CDCM7005 with external VCXO for our clocking solution which may get you ~200fs. This may get you around 57dB SNR provided you have good filters on clock and data.

    Best regards,

    Thomas Neu

    BTW I'm currently working on a big application note describing how phase noise translates into jitter and SNR degradation but in the frequency domain which makes it a little easier to understand I think. So probably another month or two and I have something to show for.

  • 0 in reply to Thomas Neu
    Prodigy 40 points

    cool,

    what kind of performance did you get at 100MSPS?  I am thinking of operating at 105MSPS. I would go 100, but that puts one of the things I want to demod right at the edge of a nyquist zone.  also, I want to distribute the ADC's clock to my FPGA board, so they sync.  is there something like the CDCE72010 for distributing clocks, or can tha CDCE72010 distribute a clock?  I haven't gotten too far into the datasheet yet. 

    also, -57 or even -54dBm is within the range what I want to do, but who doesn't want better sensitivity?  how much do you think a fixed clock would buy me, in terms of jitter/SNR?(instead of a VCO)

    do you know of any app notes on filtering clocks for this kind of stability?  I haven't done anything that requires this level of clock stability before, I wouldn't want to make some simple mistake and have to re-spin boards because of a poorly chosen/placed component.

    you should definitely post that app note here when you finish.  I will try to remember to look for it.

     

    Thanks,

    Cato

  • 0 in reply to Cato
    TI__Expert 3865 points

    Cato,

    I'm looking through some older measurements. Using the CDCE72010 and external VCXO at 122.88Msps (don't recall which VCXO) I mreasured about 53dBFS of SNR at 1GHz input. The measurements I was referring to from this week, I used a special cut Wenzel oscillator with an output frequency of ~100MHz. Measured jitter of this special oscillator was ~30fs and we achieved SNR ~61dBFS which is pretty close to the theoretical limit once you factor in aperture jitter and thermal noise of the ADC itself.

    The CDCE72010 will allow you to also fan out the clock signal to your FPGA as it has multiple outputs and individual dividers.

    There is also a couple of examples on our website where different jitter cleaner CDC devices (CDC PLL with external VCXO) are tested with different ADCs.

    Here are some examples:

    http://focus.ti.com/lit/an/scaa092/scaa092.pdf

    http://focus.ti.com/lit/an/scaa091/scaa091.pdf

     

    Tommy

     

  • 0 in reply to Thomas Neu
    Prodigy 40 points

    cool,

     

    I am getting to the point that I can actually start putting a whole design together, instead of researching bits and pieces.  I am thinking of spinning 2 antenna circuits, one for 1ghz and one for a lower frequencies (like maybe 450mhz).  what kind of SNR do you think I can get at that freq?

     

    Thanks,

    Cato

  • 0 in reply to Cato
    TI__Expert 3865 points

    Cato,

    I think it highly depends on two factors:

    1. Which ADC are you planning on using. Something like the ADS54RF63 may get you about 62dBFS (@ 1GHz IF) and ~64dBFS (@450MHz) depending on sampling rate while our ADS5474 may get you even higher SNR. Data sheet shows ~68dBFS (@450MHz IF) and ~64.7dBFS @ 1GHz IF.

    2. How good is the clock you can provide to the ADC? For the very good SNR numbers at very high IF, you probably need to shoot for jitter numbers below 70-80fs which will be very challenging.

    TI can provide you with a great performance ADC but the challenge will be to keep the phase noise under control.

    Best regards,

    Tommy