ADS931 CLK pin connection

Hi,

What is the source of your 30MHz clocking signal?  For example, are you going to have a cystal-based oscillator somwhere that sources this sampling clock, or are you deviding down a clock used in some other part of the design?  The ADS931 simply needs a single-ended clock input that meets the voltage levels for standard CMOS or TTL type of digital signals.  That is, low-level input voltage VIL should be below 0.8V and the high level input voltage VIH should be above 2.0V.  If you are using a clock from a crystal oscillator or from some digital logic family that buffers or divides down a clock signal then this clock would likely be suitable directly for input to the ADS931.

Because this clock input is used to sample the analog input signal, there are a few extra considerations for the clock to pay attention to in order to get best performance.  Any jitter on the position of the rising edge of the clock will lead to uncertainty in where exactly the sample is taken.  Note that the internal jitter (aperture jitter) of the ADS931 is typically 7ps rms, so any external jitter on the clock will combine with the internal jitter and possibly limit SNR as per equation 5 in the data sheet.  If any jitter on your clock source is gaussian, then the rms jitter of your clock will combine with the aperture jitter in a square-root-of-sum-of-squares fashion.  So you may want to select a clocking source that has low jitter, like maybe 5ps rms or better, depending on your accuracy requirements.   Also, the duty cycle of the clock is important since the low portion of the clock is used to track the value of the analog input and the high portion of the clock is used to hold the analog value for digitization.  Duty cycle may only be an issue for you if you are doing something like dividing down a higher speed clock by a factor of 3 or something like that.  The reason that the datasheet suggests a sharper rise time for the clock input is that any variation in where the clock input buffer 'sees' the clock edge go from a low-level input to a high-level input will translate into effective jitter on where the edge of the clock is seen to be.  So sharper rise times translate into less effective clock jitter.

The digital outputs from the ADS931 do not have a clock output of their own derived from the sample clock.  You need to route the sample clock to whatever logic the digital outputs go to in order to latch the digital outputs into your logic.  So if you are latching the digital data from the ADS931 into an FPGA, then you need to use the sample clock into that FPGA to clock the digital data so it is handy here that the sample clock specs are consistent with standard logic families.  The digital data output timing relative to the sample clock is shown on the bottom of page 4 of the data sheet.

Regards,

Richard P.

Hi Richard,

Thanks for your reply.

I need to sample a surge voltage signal which normally lasts for only a few milli-second... the waveform of the voltage is usually in double exponential form: exponentially rise in micro-second, peaks and then exponentially decay.... by taking consideration that 0.3 microsecond as the typical fastest signal rise time.... I think ADS931 should be able to sample the signal faithfully....

I am planning to use a 32MHz crystal oscillator (AEL1210CSN 32MHz)  to provide the clock signal.

To drive the CLK pin of ADS931, I am connect  the output pin of the oscillator to a high speed  inverter(NC7S14), then connect the output of the HS inverter to the CLK pin of ADS931.

Am I on the correct direction?

regards,

Zach

Hi,

Yes, that would supply a clock the ADS931 that would meet the electrical specifications as well as the duty cycle specifications.  I don't see a jitter spec for the AEL1210CSN, so i can't comment on whether the clock source is adequate for the SNR that you might expect for an 8bit data converter.  I note that the AEL1210CSN has a clock output that would itself be suitable for clocking the ADS931 without the inverter if the ADS931 were to operate off the same 5V supply.  Else, if the AEL1210CSN were to be on the 5V supply and the ADS931 were on a 3.3V supply then the NC7s14 could be used to on the 3.3V supply to buffer the clock to the data converter.   So yes, i'd say you are going in the right direction.  Looking at the datasheet for the NC7S14 i see the edge rate (rise/fall time) degrades a lot with capacitive loading, and you would need to use this same clock to clock your data from the ADS931 into an FPGA or whatever you are using to process the data, so i'd watch the loading on this clock line.

Regards,

Richard P.

Hey Richard,

Thanks for your comment.

I am planning to operate the ADS931 in 5V supply, and by using two 8K ohm resistors at REFT and REFB terminals, I will purposely make my analog input voltage signal swing between 2 to 3 V according to the datasheet.

Actually I am working the ADS931 with microchip PIC18F4550, but I don't think 18F4550 can process the output data from ADS931so fast at the same time.

So I plan to save the output data from ADS to a external memory first, when the short duration signal is gone, then PIC18F4550 read back the stored data and perform data manipulation.

Do you have any idea for selection of suitable data memory chip?  This is just my idea, I really don't know what memory chip is suitable for this task.

Or do you have any better suggestion to complete this task.

Thanks and regards,

Zach

Hi,

Sorry for the delay.  I've been thinking about the interface to memory.  I do not have a suggestion for a memory chip that would be a direct fit, but i rather think that an FPGA would be the best fit.  There are inexpensive FPGAs that have a fair amount of internal memory that can be used to make it look like a memory chip that is used to fill up a buffer and then the FPGA logic can also be used to unload the internal memory to whatever is going to do the processing.  I see low end FPGAs with 256Kbit of memory to 1Mbit of memory, and mid-range FPGAs with from 1Mbit to 8Mbit of memory. 

Regards,

Richard P.