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[ADC08D1520RB] - fifo 96x4k and wv5 script file

Evripidis Karseras
Intellectual 735 points
Other Parts Discussed in Thread: ADC10D1000

Dear All,

I have modified the fifos in the fpga code in order to save some space on the fpga. The changes are:

fifo_96_4k   ----> fifo_64_2k

fifo_48x16   ----> fifo_32x16

I would like to know what sort of changes are required in the script file (adc10d1000_xc4vlx25_adc08d1520rb.reg) in order to accommodate the changes in the fifo. I have found the part in the file that has to do with the acquisition part but it is uncertain as to what I am going to have to change. 

I have the feeling that nothing can be done to fix this and that it has to do with stuff hard-coded in wv5, is this the case ? If this has to do with the firmware in the cypress, is it possible to have the code ? I have read somewhere in the forum that this is not possible, has the situation changed by any chance ?

Thanks in advance,

Evros

  • 0
    TI__Mastermind 44680 points

    Hi Evros

    I'll look into this and discuss with the FPGA expert. I'll try to get an answer back by Friday.

    Best regards,

    Jim B

  • 0 in reply to Jim Brinkhurst1
    Intellectual 735 points

    Hello Jim,

    Any news on how much one can fiddle around with the GUI ? 

    -Evros

  • 0 in reply to Evripidis Karseras
    TI__Mastermind 44680 points

    Hi Evros

    I don't have much information, unfortunately. What I would suggest is trying to keep the memory reads (by the GUI/DLL) to return the same width and alignment of data even though the FIFOs are narrower. Just pad things out to the same width as the original design. Then the Wavevision DLL, script etc. should work though you'll need to be careful about choosing only the smaller capture sizes since the FIFO isn't as deep as before.

    Let me know if that makes sense.

    Best regards,

    Jim B

  • 0 in reply to Jim Brinkhurst1
    Intellectual 735 points

    Hello Jim,

    Thanks for your efforts.

    Altering the FIFO width finds the WV5/DLL unaffected since the FPGA code pads everything to 16-bits before sending it to the cypress, i.e, it works without a problem.

    Though, altering the depth as you have said works with smaller capture sizes (4K) but not with more than 8K samples which was a bit strange since the FIFO size could support it. In any case I am onto something different right now so this might not pose a problem at the moment but I might come back to this for the sake of completeness. Someone might need this later on.

    Regards,

    Evros