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ADS8881 maximum SCLK

Craig Hillis
Intellectual 480 points
Other Parts Discussed in Thread: ADS8881, ADCPRO, ADS8860, ADS8861

The data sheet for the ADS8881 states that the maximum SCLK frequency is 66.666MHz (15ns minimum period). The ADS8881 EVM has a default SCLK of 80MHz.

Is the ADS8881EVM violating the part spec, of is there an error in the data sheet?

  • 0
    Expert 2585 points

    Hi Craig,

    As I see the 80MHz is the maximum clock frequency for SPI interface which could be set for Mother board (MB0) of the ADS8881PDK. MB0 is the universal board  which is used with different ADC and the clock which could be generate by it is defined by the firmware.

  • 0 in reply to Oleksiy Pazyuk
    Intellectual 480 points

    When I measure the SCLK to the ADS8881 on the ADS8881EVM it is at 80MHz. This is the signal going to the ADC.

  • 0 in reply to Craig Hillis
    Intellectual 480 points

    When I set the SCLK in ADCPro to 66.66MHz it changes it to 67MHz and the maximum data rate is 966.086lHz. This then reduces the clock to the ADC to 67MHz but also reduces the sample rate to 966.086MHz.

    In order to run the ADC at the full specified rate the ADS8881EVM used a 80MHz clock for SCLK to the ADC.

  • 0 in reply to Craig Hillis
    Intellectual 480 points

    Is there any further information on why the ADS8881EVM clocks the chip at 80MHz when the data sheet for the ADS8881 lists a maximum clock rate of 66.667MHz?

    Also, based on the data sheet for the ADS8881, to run it at its claimed 1MS/s, the accuracy of the clocks would have to be 0ppm.

    Can TI provide a parts list of components that will run the ADS8881 at the claimed 1MHz and still meet the data sheet timing requirements?

  • 0 in reply to Craig Hillis
    TI__Expert 6925 points

    Hello Craig,

    The ADS8881 is fast enough at room temperature to allow 80MHz, but over operational temperature range, sclk should be slower as specified in sclk max of the datasheet.

    We realized the tight timing 66.6MHz sclk max creates, so we re-analyzed the limitations of the SCLK over operational temperature finding that 66.6MHz isn’t the maximum frequency that the ADS8881 allows. The revised over temperature maximum sclk is 70MHz, and it will be updated in the datasheet in about a month. The user guide will be revised to note this change as well.

    Therefore, the EVM software should be configured with 70MHZ and 1MSPS as shown:

    Best regards,
    Rafael 

  • 0 in reply to Rafael Ordonez
    Intellectual 480 points

    Thanks for the update.

    Are the data valid timings in Table 1. TIMING REQUIREMENTS: 3-Wire Operation going to change?

    Specifically:

    th-CK-DO SCLK falling edge to current data invalid 3 ns min

    td-CK-DO SCLK falling edge to next data valid delay 13.4 ns max

    td-CNV-DO Enable time: CONVST low to MSB valid 12.3 ns max

    These can make it difficult to know what data you are clocking if you are using the maximum SCLK frequency. The maximum delay is almost equal to the clock period meaning that unlike the data sheet claim the data is not necessarily valid on the rising edge of the next clock. It appears that you have to use the falling edge of SCLK and the 3ns minimum data valid after falling edge of SCLK is enough.

  • 0 in reply to Craig Hillis
    TI__Expert 6925 points

    Hello Craig,

    The current datasheet states that both edges could be used to read out data, and as you mention, it doesn’t apply for fast SCLK frequencies due to data delays. However, it does apply for SCLK frequencies slower than 37.3MHz as illustrated in the following image for slower sampling rates:

     

    Although datasheet timing diagrams imply that data should be read in subsequent falling edges for fast SLCK, the written explanation is missing this important distinction for SCLK frequencies faster than 37.3MHz, which apply to the ADS8881, ADS8861, and ADS8860. For example, the following diagram shows what you mentioned regarding the need to use subsequent falling edges to accommodate the data delays:

     

    Therefore, in the current revision, besides of SCLK update, we will be including a clearer explanation in the datasheet regarding reading edges for fast and slow SCLK frequencies for the ADS8881, ADS8861, and ADS8860.

    Thank you,
    Rafael